[Arm-netbook] help needed with a ttl logic circuit

[Luke Kenneth Casson Leighton]

hi folks could someone please help analyse this circuit to see if it is correct?

Loading Image...

the requirement:

* an STM32F's "BOOT0" is, by default "pulled to GND" in order that
"normal" operation happens

* the boot operation needs to be selectable by a GPIO from a main CPU
(TTL, with a different voltage)

* if however the main CPU's GPIO is *DISCONNECTED*, "normal" operation
of the STM32F is required.

so, the main things here are:

* the STM32F is run from a 3.3v supply

* the CPU can be a totally different TTL voltage level from the
STM32F. it could be 5.0V, it could be 3.3v, it could be 3.0v, it
could be even 1.8v.

* the default behaviour needs to be "pull to GND", even if the input
is floating.


R28 ensures that the transistor is, by default, ON, so that R2 is
connected to GND and thus BOOT0 operates in "normal" mode.

however current will flow from EXT_BOOT0 if it is "high", which would
start fighting with VCC_SYS_3V3 if EXT_BOOT0 is over 3.3v, so D1 stops
that from happening.

i think i'm stuck though when it comes to pulling EXT_BOOT0 down to
"GND" because actually it will be TTL 0.7v (or so), which, when the
diode is taken into account (another 0.7v), i don't think it's enough
to switch off the transistor.

... so.... help! what do i do?

tia,

l.

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[Ralf-Peter Rohbeck via arm-netbook]

You could use two transistors in a darlington configuration or add a
diode and a resistor to the base of the transistor. Either would cause
an effective 1.4V VBE needed to turn the transistor on. OTOH with a
Germanium or Schottky diode you should be OK as long as EXT_BOOT0 is a
CMOS output because it'll go to almost 0V if the current is low. Not
sure what the levels might be. Even a nominally TTL output should go
much lower than 0.7V at low current.

Post by Luke Kenneth Casson Leighton
hi folks could someone please help analyse this circuit to see if it is correct?
http://hands.com/~lkcl/ttl_logic_circuit.png
* an STM32F's "BOOT0" is, by default "pulled to GND" in order that
"normal" operation happens
* the boot operation needs to be selectable by a GPIO from a main CPU
(TTL, with a different voltage)
* if however the main CPU's GPIO is *DISCONNECTED*, "normal" operation
of the STM32F is required.
* the STM32F is run from a 3.3v supply
* the CPU can be a totally different TTL voltage level from the
STM32F. it could be 5.0V, it could be 3.3v, it could be 3.0v, it
could be even 1.8v.
* the default behaviour needs to be "pull to GND", even if the input
is floating.
R28 ensures that the transistor is, by default, ON, so that R2 is
connected to GND and thus BOOT0 operates in "normal" mode.
however current will flow from EXT_BOOT0 if it is "high", which would
start fighting with VCC_SYS_3V3 if EXT_BOOT0 is over 3.3v, so D1 stops
that from happening.
i think i'm stuck though when it comes to pulling EXT_BOOT0 down to
"GND" because actually it will be TTL 0.7v (or so), which, when the
diode is taken into account (another 0.7v), i don't think it's enough
to switch off the transistor.
... so.... help! what do i do?
tia,
l.
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[Luke Kenneth Casson Leighton]

On Sat, Aug 22, 2015 at 10:27 PM, Ralf-Peter Rohbeck via arm-netbook

Post by Ralf-Peter Rohbeck via arm-netbook
You could use two transistors in a darlington configuration

just reading about that here:
http://www.electronics-tutorials.ws/blog/relay-switch-circuit.html

Post by Ralf-Peter Rohbeck via arm-netbook
or add a diode
and a resistor to the base of the transistor. Either would cause an
effective 1.4V VBE needed to turn the transistor on. OTOH with a Germanium
or Schottky diode you should be OK as long as EXT_BOOT0 is a CMOS output
because it'll go to almost 0V if the current is low. Not sure what the
levels might be. Even a nominally TTL output should go much lower than 0.7V
at low current.

ralf, really appreciate the response. any chance you could find a
random image on the internet as a demo circuit, or perhaps draw it out
for me?

at the moment i'm considering using a 2nd transistor, powered from
the other board (yes it'll be TTL - just with a different voltage).

basically this design is split into two boards, one is the EOMA68
main PCB with the CPU Card: i'd like the CPU Card to control the boot
process (for firmware re-flashing) of the STM32F072, which is on the
2nd PCB.

but, if the PCB is disconnected for any reason (testing purposes) i'd
like it to operate "stand-alone", powering up in "normal operation",
which requires that BOOT0 be connected to GND with e.g. a 10k
resistor.

the different TTL voltages that the CPU card(s) can operate at is
what's the key issue, and, also, i don't want to put in another pin to
send over the TTL REF voltage over to the STM32F072 board (unless
absolutely necessary).

what i'm currently thinking is, put one transistor on the one PCB and
another one one the other. in effect a "buffer" circuit.

mmmm.... also.... just checking the datasheet (DM00090510 section
6.3.14) it says that BOOT0's threshold level is "0.3 * (VIN) - 0.3".
that works out at 0.69 volts, so anything with a standard 0.7v
diode... wark-wark :)


ARGH you know what? i'm just going to say if normal operation is
needed in stand-alone, put a jumper across EXT_BOOT0 :)

i'll redo the circuits in a mo....

l.

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[Luke Kenneth Casson Leighton]

ok so i redid it, using a darlington pair, because yes the voltage
definitely needs to be below 0.69v at the output: also, forget about
the "disconnected" operation, that can be done with a jumper.

Loading Image...

still don't feel completely happy (esp. with the schottky diode), i
feel another transistor might be needed especially because VREFTTL
(for the EOMA68_BOOT0 TTL level) could be *lower* than 3.3v.

l.

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[Dominique Dumont]

Post by Luke Kenneth Casson Leighton
http://hands.com/~lkcl/ttl_logic_circuit2.png
still don't feel completely happy (esp. with the schottky diode), i
feel another transistor might be needed especially because VREFTTL
(for the EOMA68_BOOT0 TTL level) could be *lower* than 3.3v.

There's no resistor to limit the current when ext_boot0 is up (from ext_boot0
to gnd).

But the schottky diode will prevent any current to go there... I don't see how
the first transistor can be switched on...

[Dominique Dumont]

Post by Luke Kenneth Casson Leighton
still don't feel completely happy (esp. with the schottky diode), i

I think it can be done with 3 resistors and 1 transistor used with a floating
collector. Using a floating collector is better because CPU voltage can be
lower than 3.3v.

I've attached a png file with a proposal. You may need to adjust the resistor
values depending on the current drawn from the CPU.

When the input is floating, the transistor is on because of the 100k pull-up.

When the input is 3.3, the transistor is also on.

When the input is 0, the transistor emitter is driven to ~ 0.3V which should
switch off the transistor.

When the transistor in switched on, in a saturated state, the voltage between
collector and emitter is much lower than 0.6V, so the CPU will see a logical
0. When the transistor is off, the output is high impedance. You may need a
pull-up resistor on the CPU board.

Please take this with a grain of salt, it's been a while since I played with
transistors this way (~ 25 years...)

Hope this helps.

[Dominique Dumont]

Post by Dominique Dumont
When the input is 0, the transistor emitter is driven to ~ 0.3V which
should switch off the transistor.

Even better, the emitter can be driven to 0 V bby putting the 100k resistor
before the 10k. (attached png)

Hope this helps

[Luke Kenneth Casson Leighton]

Post by Dominique Dumont

Post by Dominique Dumont
When the input is 0, the transistor emitter is driven to ~ 0.3V which
should switch off the transistor.

Even better, the emitter can be driven to 0 V bby putting the 100k resistor
before the 10k. (attached png)
Hope this helps

yeay :)

ok so i looked up the datasheet for the 2N3904:
http://www.mouser.com/ds/2/149/2N3904-82270.pdf

collector-to-emitter is ~0.3 volts, base-to-emitter is 0.65 maybe as
high as 0.95 volts.

i'm horribly confused, now. i thought i knew how transistors worked!

this circuit (in the section "serial") looks much more obvious, to
me. and the Rds(ON) for low current is reported to be around 0.09v.
http://people.physics.anu.edu.au/~dxt103/472/wspr_tx/

l.

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[Luke Kenneth Casson Leighton]

ralf, dominique, phil: i believe this is what i'm looking for, let me
try and work through it, see if i got it right:

Loading Image...

except, the 1st transistor will be supplied by VREFTTL (from the CPU)
and the 2nd is supplied by VCC-3V3 (from the STM32F).

the 1st transistor is against the flow of current in the instance
where VREFTTL is less than VCC-3V3.

when the input is at 0V:

* 1st transistor goes "on", so current flows through the 1st resistor
(at VREFTTL). however the collector sits at 0.7v.
* the implications of that for the 2nd transistor is: it can't switch on.
* therefore, the 2nd transistor, being "off", has its own resistor up
at VCC-3V3.

when the input is at VREFTTL (or close to it):

* 1st transistor is "off", *BUT* is acting as a diode from base to collector.
* this results in (VREFTTL-0.7v) going into the 2nd transistor's base
* that makes the 2nd transistor switch ON
* that results in current flow across the 2nd transistor
* that makes the saturation voltage from collector to emitter 0.3v
which is what's needed to have BOOT0 at CMOS logic level "0".

anyone see any flaws?

l.

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[Luke Kenneth Casson Leighton]

ok so like this:
Loading Image...

l.

p.s. i definitely do not want to go to this kind of complexity / completeness:
http://www3.eng.cam.ac.uk/DesignOffice/mdp/electric_web/Digital/DIGI_3.html

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[Dominique Dumont]

Post by Luke Kenneth Casson Leighton
anyone see any flaws?

It should work.

But I don't see why the first transistor is needed. Well, it's only a few
cents...

All the best

[Luke Kenneth Casson Leighton]

Post by Dominique Dumont

Post by Luke Kenneth Casson Leighton
anyone see any flaws?

It should work.
But I don't see why the first transistor is needed.

it stops the back-voltage down the 2nd resistor (top right-side,
connected to 3.3V) into the CPU (VREFTTL). imagine that VREFTTL is
1.8v, and the transistor wasn't there: the *entire CPU* would be
powered from that resistor at well above the CPU's rated voltage.

with a 28nm CPU, it would be irreversibly damaged by the over-voltage
coming back down that resistor.

can't have that!

Post by Dominique Dumont
Well, it's only a few
cents...

:)

Post by Dominique Dumont
All the best
--
https://github.com/dod38fr/ -o- http://search.cpan.org/~ddumont/
http://ddumont.wordpress.com/ -o- irc: dod at irc.debian.org
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[Ralf-Peter Rohbeck via arm-netbook]

Yes that's what I'd use. You'll still need a 100k pull-up from EXT_BOOT0
to VCC to keep the transistors on when EXT_BOOT0 is disconnected or high.
You don't need the high beta of the combined transistors, just the
increased VBE, so you could replace Q1 with a silicon diode with the
anode on EXT_BOOT0 and the cathode on B of Q3.

Post by Luke Kenneth Casson Leighton
ok so i redid it, using a darlington pair, because yes the voltage
definitely needs to be below 0.69v at the output: also, forget about
the "disconnected" operation, that can be done with a jumper.
http://hands.com/~lkcl/ttl_logic_circuit2.png
still don't feel completely happy (esp. with the schottky diode), i
feel another transistor might be needed especially because VREFTTL
(for the EOMA68_BOOT0 TTL level) could be *lower* than 3.3v.
l.

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[Daniel Serpell]

Hi!

On Sat, Aug 22, 2015 at 2:21 PM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
hi folks could someone please help analyse this circuit to see if it is correct?
http://hands.com/~lkcl/ttl_logic_circuit.png
* an STM32F's "BOOT0" is, by default "pulled to GND" in order that
"normal" operation happens
* the boot operation needs to be selectable by a GPIO from a main CPU
(TTL, with a different voltage)
* if however the main CPU's GPIO is *DISCONNECTED*, "normal" operation
of the STM32F is required.
* the STM32F is run from a 3.3v supply
* the CPU can be a totally different TTL voltage level from the
STM32F. it could be 5.0V, it could be 3.3v, it could be 3.0v, it
could be even 1.8v.
* the default behaviour needs to be "pull to GND", even if the input
is floating.

A little late to the discussion, but I would use something like:
https://github.com/sparkfun/Logic_Level_Bidirectional

The schematic is here:
https://cdn.sparkfun.com/datasheets/BreakoutBoards/Logic_Level_Bidirectional.pdf

To assure that the output is low when the LV input is disconnected,
you could add a
resistance from the input to ground, I would use a 2k resistor, so
that at 1.8V the
gate has 1.5V, setting a low state in the output.

This circuit is cheap, and you would use only 3 resistors and one FET.

Daniel.

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[Luke Kenneth Casson Leighton]

On Tue, Aug 25, 2015 at 12:31 AM, Daniel Serpell

Post by Daniel Serpell
Hi!
On Sat, Aug 22, 2015 at 2:21 PM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
hi folks could someone please help analyse this circuit to see if it is correct?
http://hands.com/~lkcl/ttl_logic_circuit.png
* an STM32F's "BOOT0" is, by default "pulled to GND" in order that
"normal" operation happens
* the boot operation needs to be selectable by a GPIO from a main CPU
(TTL, with a different voltage)
* if however the main CPU's GPIO is *DISCONNECTED*, "normal" operation
of the STM32F is required.
* the STM32F is run from a 3.3v supply
* the CPU can be a totally different TTL voltage level from the
STM32F. it could be 5.0V, it could be 3.3v, it could be 3.0v, it
could be even 1.8v.
* the default behaviour needs to be "pull to GND", even if the input
is floating.

https://github.com/sparkfun/Logic_Level_Bidirectional
https://cdn.sparkfun.com/datasheets/BreakoutBoards/Logic_Level_Bidirectional.pdf
To assure that the output is low when the LV input is disconnected,
you could add a
resistance from the input to ground, I would use a 2k resistor, so
that at 1.8V the
gate has 1.5V, setting a low state in the output.
This circuit is cheap, and you would use only 3 resistors and one FET.

ta daniel, yes i saw this circuit around in the exploration i've been doing.

the only problem i have with it is this:

when the input is at 0V, i assume that means that the other side of
the MOSFET also goes to 0V (plus a little bit - say 0.1V).

however if the input were to go to, say.... 0.6V (because that's
within TTL levels), then the output would *also* go to 0.6V, plus a
little bit, that's 0.7v.

.... and it's *way* over the acceptable threshold for BOOT0, which is
a full 0.3 volts *lower* than CMOS. in this case (with a 3.3v supply)
it's 3.3 * 0.3 - 0.3 which is 0.69v...

that's *barely* within tolerance.

so i feel that some additional transistor or other components are
needed when using the MOSFET in order to make sure that the input is
definitely definitely pulled right down.

i may be wrong here, please do tell me if i am.

Post by Daniel Serpell
You don't need the high beta of the combined transistors,

i'm not sure what high beta is, but the output definitely needs to go
below 0.69 volts in order to trigger BOOT0 ROM mode. would the
suggested circuit (with the silicon diode) do that?

thanks all,

l.

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[Daniel Serpell]

Hi!,


On Mon, Aug 24, 2015 at 9:45 PM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Tue, Aug 25, 2015 at 12:31 AM, Daniel Serpell

Post by Daniel Serpell
https://cdn.sparkfun.com/datasheets/BreakoutBoards/Logic_Level_Bidirectional.pdf
To assure that the output is low when the LV input is disconnected,
you could add a
resistance from the input to ground, I would use a 2k resistor, so
that at 1.8V the
gate has 1.5V, setting a low state in the output.
This circuit is cheap, and you would use only 3 resistors and one FET.

ta daniel, yes i saw this circuit around in the exploration i've been doing.
when the input is at 0V, i assume that means that the other side of
the MOSFET also goes to 0V (plus a little bit - say 0.1V).
however if the input were to go to, say.... 0.6V (because that's
within TTL levels), then the output would *also* go to 0.6V, plus a
little bit, that's 0.7v.

No, it will be higher, because in that case the MOSFET would turn off
a little more and it's resistance would go up (1.8V at LV minus 0.6V =
1.2V at gate).

But I don't understand why you are talking about "TTL" levels here, as:
1) I could not think on any way that an old TTL output device would be
connected to that input.
2) TTL devices had about 0.2V output, with relatively high current output.

In fact, the problem with TTL devices was that the HIGH output had low
current capability, so you need to assure that the HIGH input threshold
was low enough to allow for the low driving currents.

In your case, you need the input to toggle on a variable voltaje digital
output, (1.8V or 2.5V or 3.3V), the good thing about the N-FET circuit
is that the high threshold is automatically set at about 1V less than the
power supply voltage, so as long as the "LV" input is connected to
the low voltage supply and the HV input connected to the high voltage
supply, the conversion will work.

Daniel.

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[Luke Kenneth Casson Leighton]

On Tue, Aug 25, 2015 at 4:18 AM, Daniel Serpell

Post by Daniel Serpell
Hi!,
On Mon, Aug 24, 2015 at 9:45 PM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Tue, Aug 25, 2015 at 12:31 AM, Daniel Serpell

Post by Daniel Serpell
https://cdn.sparkfun.com/datasheets/BreakoutBoards/Logic_Level_Bidirectional.pdf
To assure that the output is low when the LV input is disconnected,
you could add a
resistance from the input to ground, I would use a 2k resistor, so
that at 1.8V the
gate has 1.5V, setting a low state in the output.
This circuit is cheap, and you would use only 3 resistors and one FET.

ta daniel, yes i saw this circuit around in the exploration i've been doing.
when the input is at 0V, i assume that means that the other side of
the MOSFET also goes to 0V (plus a little bit - say 0.1V).
however if the input were to go to, say.... 0.6V (because that's
within TTL levels), then the output would *also* go to 0.6V, plus a
little bit, that's 0.7v.

No, it will be higher, because in that case the MOSFET would turn off
a little more and it's resistance would go up (1.8V at LV minus 0.6V =
1.2V at gate).

ok. so.... if the input was at 0V the output would go to... what?
if it's above 0.69v, then that level-shifting circuit can't be used
as-is. BOOT0 simply wouldn't be enabled: it requires below 0.69v when
the STM32F072 is operated at 3.3v.

Post by Daniel Serpell
1) I could not think on any way that an old TTL output device would be
connected to that input.
2) TTL devices had about 0.2V output, with relatively high current output.

i needed a specification for EOMA68, so i picked one. TTL seemed
like a good idea. we're still in "development" phase so an
alternative could be picked... i don't mind changing it to e.g. CMOS
now that there's a VREFTTL.

Post by Daniel Serpell
In fact, the problem with TTL devices was that the HIGH output had low
current capability, so you need to assure that the HIGH input threshold
was low enough to allow for the low driving currents.

hmmm ok. so putting CMOS as the specification would be better.

Post by Daniel Serpell
In your case, you need the input to toggle on a variable voltaje digital
output, (1.8V or 2.5V or 3.3V),

.... which needs to be specified, then every possible combination verified...

unfortunately this isn't like a "normal" electronics single-board
design ( make a decision, pick a CPU, pick an EC, test a couple of
voltages and then forget about it).

it's a bit of a risk developing with only one threshold voltage (most
of the SoCs i've used have been 3.3v) but all the circuits need to
cater for variable future VREFTTL.

whatever is picked, though, this particular circuit has an added
wrinkle. even if CMOS is picked as the EOMA68 GPIO specification, it
cannot be assumed that the low voltage *will* be reached, it has to be
assumed worst-case i.e. that the low voltage will be 0.3*VREFTTL
(which in the case of 3.3v will be 0.99v).

BOOT0 has that *different* low threshold from the rest of the [CMOS]
STM32F072 GPIO pins: the formula is 3.3 * 0.3 - 0.3.

so whatever circuit is used, it *must* output a voltage *below* 0.69v
even when its input is between 0 and 0.99v... when VREFTTL is 3.3v.

i think... i have one pin spare: i think it might be a good idea to
send over VREFTTL to the board and look at a unidirectional level
shifter IC.

l.

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[Luke Kenneth Casson Leighton]

this one. perfect :) and ends up at $0.15 in 1k volumes, which is tolerable.

http://www.ti.com/lit/ds/symlink/sn74lv1t34.pdf

table 4.5 electrical characteristics show a wide range of (suitable)
Hi-in and Low-in voltages, depending on the supply input current.

then, for the 3.3v output side... the critical one V-out-low iiis....
maximum of 0.2v yay! even if 4.5v was used it would still be a 0.35v
output. V-out-high is

i know it's not the same as a one or two $0.02 transistors/FETS. i've
seen some tutorials online that explain the operation of "proper"
buffer circuits like this one, it's a mad number of components: 5 or 6
transistors, 3 diodes, 4 resistors, just to ensure fully-on and
fully-off...

ooo wait a minute!
https://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic#Fundamental_TTL_gate

dominique, if you look at that section, it explains that the first
transistor is in "reverse-biasing" mode when the inputs are high.
later on that section says that when the 1st transistor goes through
its "active" region it very quickly draws current away from the base
of the output transistor. means "fast switching".

oooo i'm tempted to use that.... :)

l.

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