Richard Wilbur
2017-08-03 11:37:21 UTC
HDMI Layout Notes
for EOMA68 Cards
by Richard Wilbur
Impedance
Trace Impedance:
100 Ohm +/-15% differential[11][12], 55 Ohm +/-15% single-ended[3]
(90 Ohm +/-15% differential, 50 Ohm +/-15% single-ended[3])
There seems to be some small disagreement between sources on the
differential trace impedance for HDMI high-speed signals.
Chrontel[11], Texas Instruments[12], and JAE[13] all quote 100 Ohm but
with different tolerances--Chrontel +/-10%, Texas Instruments +/-15%,
JAE +/-25% (in connector area[13])--while Toradex[3] quotes the goal
as 90 Ohm +/-15%. These ranges overlap but the normal variation in
manufacturing is more likely to exceed the limits of the acceptable
range if we design to the wrong goal!
90 Ohm +/-15% = [76.5, 103.5] Ohm
100 Ohm +/-15% = [85, 115] Ohm
It seems the consensus is on 100 Ohm +/-15% for the differential impedance.
Toradex mentions something else which helps with the selection of
design parameters: "The differential impedance is always smaller than
twice the single-ended impedance"
Z(differential) < 2 * Z(single-ended)[14]
=> Z(single-ended) > Z(differential) / 2
Thus, if we wish to have Z(differential) = 100 Ohm +/-15%, we should
choose the single-ended impedance such that
Z(single-ended) > (100 Ohm +/-15%) / 2 = 50 Ohm +/-7.5%
Toradex suggests 55 Ohm single-ended impedance to coincide with 100
Ohm differential impedance.[15]
In order to model and calculate expected impedance we need to describe
the geometry of the arrangement of traces, reference planes, and
dielectric layers in the PCB.
PCB Dimensions (not drawn to scale or even to correct aspect ratio):
______
^
T (thickness of copper in signal layer)
v
_______________________________
^
H (thickness or height of insulator)
v
_______________________________
reference plane (GND or Power)
_______________________________
The 6-layer FR-4 PCB chosen for EOMA68-A20 has the following
characteristic dimensions:
total thickness of PCB = 1.2mm ~= 47.3mil
H(height of dielectric between outer copper layer and adjacent
reference plane) = 6.4mil
copper cladding = 1oz
min{W(trace width)} = 5mil
min{S(trace-to-trace space)} = 5mil
min{diameter(plated through-hole vias)} = 6mil
diameter(via surround/pad) = 12mil
To calculate the thickness (T) of 1 ounce copper requires several
conversion factors and the density of copper. "1 ounce copper" refers
to the thickness of 1 ounce (avoirdupois versus troy) of copper spread
over 1 square foot. There is at least one web site which purports to
calculate the thickness in mils of a particular weight of copper
cladding[16], but they use some pretty heavy approximations for
otherwise well-known conversion factors and conclude that 1.37 mil = 1
oz Cu. I used the standard unit conversion factors as shown below:
Given:
Areal density = 1 oz Cu / ft^2
Exact conversion factors:
1 (avoirdupois) oz = 28.349523125g [17]
1 ft^2 = (1ft * 12in/1ft * 2.54cm/1in)^2 = (30.48cm)^2
Empirical value:
Density (Cu pure) rho = 8.96 g / cm^3 [18][19: CRC, LNG]
Calculation:
T = areal density(given) * conversion(oz->g) / (volume density) /
conversion(ft->cm)^2[16]
T = 1 oz Cu / ft^2 * 28.349523125g / 1 oz * 1 cm^3 Cu / 8.96 g Cu * 1
ft^2 / (30.48cm)^2
= 0.003405711cm Cu = 0.03405711mm * 1in / 25.4mm * 1000mil / 1in = 1.34mil Cu
(Using 8.92 gCu / cm^3 [19: WEL] => T = 1.35mil Cu)
The most well-attested value for copper's density was 8.96 g/cm^3
yielding T = 1.34mil Cu. Illustrating the sensitivity of the
calculation to variation of parameters, the minority density value of
8.92 g/cm^3 yielded T = 1.35mil Cu.
Microstrip PCB Dimensions (not drawn to scale or even to correct aspect ratio):
<-W-><--- S ---><-W-><----- D ----->
__IIIII___________IIIII___________________IIIII
Signal:+ - x
W = design width of trace
S = spacing between traces of differential pair (+,-)
D = spacing to unrelated signal "x" (another pair, ground shield, etc.)
Texas Instruments gives some equations to help calculate trace
geometries for 100 Ohm differential impedance.[12]
Z(differential) = 2 * Z(single-ended) * (1 - 0.48 * exp(-0.96 * S / H))
Z(single-ended) = 88.75/sqrt(relative permittivity + 1.47) * ln(5.97 *
H / (0.8 * W + T))
Since the board material and manufacturing process specify the parameters:
relative permittivity(FR-4) = 4.4[1]
H = 6.4mil
T = 1.34mil
and the HDMI standard specifies:
Z(differential) = 100 Ohm
we have two equations in three unknowns:
Z(single-ended), W, S
Given the guidance that Z(single-ended) > 50 Ohm, we can solve the
second equation for W(Z(single-ended)),
W<mils> = 7.463 * H * exp(-Z(single-ended) * sqrt(relative
permittivity + 1.47) / 88.75) -1.25 * T
Then select a value for Z(single-ended), turn the crank and see what
value of W we come up with. After looking at the result we may decide
to select a different value for Z(single-ended) and calculate the
concomitant W in order to find a routable trace width and a usable
single-ended impedance.
Let's try this for Z(single-ended) = 55 Ohm.
W(Z(single-ended) = 55 Ohm) = 7.463 * 6.4mil * exp (-55 Ohm * sqrt(4.4
+ 1.47)/88.75) - 1.25 * 1.34mil
= 8.97mil
Then we can solve the equation that gives differential impedance for
S, plug in our values for single-ended and differential impedance and
see what trace-spacing (S) we get.
S = -H / 0.96 * ln((2 * Z(single-ended) - Z(differential)) / 0.96 /
Z(single-ended))
S(Z(single-ended) = 55 Ohm) = -6.4mil / 0.96 * ln((2 * 55 Ohm - 100
Ohm) / 0.96 / 55 Ohm)
= 11.1mil
The distance, D, to adjacent signal pairs and shield traces is suggested to be,
D >= 3 * S[12]
with the caveat that running a ground shield trace on only one side
can create an imbalance that increases EMI. "Ground trace shields
should have a scattering of vias to the underlying ground plane."[12]
Z(single-ended) W<mil> S<mil> min{D}<mil>
<Ohm>
51 10.2 21.3 63.9
55 8.97 11.1 33.3
60.1 7.58 7.00 21.0
64.6 6.51 5.02 15.1
Table of single-ended impedances and associated trace width and
spacing.[These numbers are based on formulas which are approximations
with error bounds of +/-10%.][12]
Here we can see the effect of changing the single-ended impedance on
width and spacing of traces in a differential pair of given
differential impedance. By raising the single-ended impedance we
reduced both the width of the traces and also the spacing. The other
outgrowth is that the common-mode rejection is improved by lowering
the single-ended impedance of the traces. Common-mode signal stems
from other signals (EMI) coupled into the traces, uncompensated
intra-pair skew, and imperfect differential signal drivers at the
source. Common-mode signal will radiate (EMI) from circuit board
traces. So we have a trade-off to consider:
1. We can minimize common-mode signal by lowering single-ended
impedance which increases the trace width and spacing for a given
differential impedance.
2. This is limited by the fact that, for a microstrip differential
pair, the single-ended impedance is greater than half the differential
impedance.
Looking at the single-ended impedance values, the difference between
51 Ohm and 64.6 Ohm is an increase of less than 30% and thus won't
drastically change the common-mode performance, so my inclination if
you're strapped for space would be to use the higher single-ended
impedance with 6.5mil wide traces spaced apart 5mils and try for
15mils between pairs.
Reviewing with reference to TI's "Routing Guidelines"[20]:
i. Use the smallest trace spacing possible, which usually is
specified by your PCB vendor: in our case 5 mils
ii. Make sure the geometries obey:
a. S < H; (S = 5mil) < (H = 6.4mil)
b. S < W; (S = 5mil) < (W = 6.5mil)
c. W < 2H; (W = 6.5mil) < (2H = 12.8mil)
d. D > 2S = 10mil
Looks like we abide by their guidelines if we use the 64.6 Ohm
single-ended impedance values. It seems the distance, D, to the next
trace is somewhat flexible because in this reference it is reduced
from 3S to 2S. (I'm sure 3S is better than 2S, if you have the
space.)
Ground Planes under Pads
Toradex mentions the lower impedance between wide traces and the
reference plane causing impedance mismatch at large pads for
components and connectors.[21] The width of the pads in the
illustration are 5-6x the width of the traces connecting to them. On
the micro-HDMI connector the width of the pads is around 0.2mm (JAE
DC3R019JA7R1500 pad width = 0.23 +/-0.03 mm ~= 9.1 +/- 1.1 mil), where
the smallest trace we can have is 5 mil thus our greatest proportion
is 10.2 mil / 5 mil ~ 2. So this is probably less of a problem than
if the pads were 5-6 times the width of our traces. In fact if we
compare the dimensions of the connector pads and spacing (which is
about the same as pad width) to those of the trace width and spacing
for 55 Ohm single-ended impedance in the table above, they nearly
match. Thus I don't think this will be a big issue for this board
because while the pads are wider than our traces, they're spaced about
as far apart as we would space traces that are that wide to still get
100 Ohm differential impedance.
Via Impedance
If and when we start supporting HDMI v2.0+ we will need to tune the
impedance of our signal vias even more keenly as our signals will
surpass the 10GHz barrier.[22] Presently we also have the happy
situation that since our high-frequency signal vias always connect
between top and bottom layers, our stub length is 0 on signal vias.
Creating transparent (tuned) vias requires familiarity with a 3-D EM
simulator and some time to set up, run, evaluate results of
simulations, and then repeat in order to tune the impedance. (See
section below "Libre Field Solvers".)
We can still take some of the recommendations to heart:
1. Use minimal size vias for high-frequency traces to reduce
parasitic capacitance.[23]
2. Place the two vias of the differential pair in close proximity to
increase capacitive coupling between the signals.(smaller via pitch)
3. Instead of using two separate anti-pads on signal vias, combine
them into oval shared antipads (on every layer) to reduce parasitic
capacitance.
4. Place ground vias next to signal vias to provide ground-return
paths.[22, Figure 2]
References:
[1] https://en.wikipedia.org/wiki/FR-4
[2] Toradex, page 21
[3] Toradex, page 38
[4] TI, page 4
[5] Chrontel, page 5
[6] https://forum.allaboutcircuits.com/threads/hdmi-inter-intra-pair-skew-inter-pair-synchronization.75801/
[7] https://e2e.ti.com/support/interface/high_speed_interface/f/138/t/267205
[8] https://www.researchgate.net/publication/224650488_Effects_of_skew_on_EMI_for_HDMI_connectors_and_cables
[9] Toradex, page 17, Figures 12 & 13
[10] Toradex, pages 22-23
[11] Chrontel, page 4
[12] TI, page 5
[13] JAE, page 1
[14] Toradex, page 12
[15] Toradex, page 13, Table 3
[16] http://referencedesigner.com/cal/cal_02.php
[17] https://en.wikipedia.org/wiki/Ounce#International_avoirdupois_ounce
[18] https://en.wikipedia.org/wiki/Copper
[19] https://en.wikipedia.org/wiki/Densities_of_the_elements_(data_page)
[20] TI, page 8
[21] Toradex, pages 18-19, Figure 16
[22] https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs-four-things-you-need-to-know-about-vias
[23] TI, page 9
Bibliography:
Chrontel: Application Note AN-B026, "PCB Layout and Design Guide for
CH7101A HDMI to VGA Converter",
http://www.chrontel.com/media/Application%20Notes/AN-B026%20Rev0.2.pdf
Japan Aviation Electronics Industry, Ltd. (JAE): "HDMI Standard Type
D HDMI Micro Connector: DC3 Series", Connector MB-0233-2, May 2013,
http://www.jae.com/z-en/pdf_download_exec.cfm?param=MB-0233-2E_DC3.pdf
Texas Instruments (TI): "HDMI Design Guide", High-Speed Interface
Products, June 2007,
http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-138-01-00-00-10-65-80/Texas-Instruments-HDMI-Design-Guide.pdf
Toradex: "Layout Design Guide", v1.0, 14 April 2015,
http://docs.toradex.com/102492-layout-design-guide.pdf
_______________________________________________
arm-netbook mailing list arm-***@lists.phcomp.co.uk
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for EOMA68 Cards
by Richard Wilbur
Impedance
Trace Impedance:
100 Ohm +/-15% differential[11][12], 55 Ohm +/-15% single-ended[3]
(90 Ohm +/-15% differential, 50 Ohm +/-15% single-ended[3])
There seems to be some small disagreement between sources on the
differential trace impedance for HDMI high-speed signals.
Chrontel[11], Texas Instruments[12], and JAE[13] all quote 100 Ohm but
with different tolerances--Chrontel +/-10%, Texas Instruments +/-15%,
JAE +/-25% (in connector area[13])--while Toradex[3] quotes the goal
as 90 Ohm +/-15%. These ranges overlap but the normal variation in
manufacturing is more likely to exceed the limits of the acceptable
range if we design to the wrong goal!
90 Ohm +/-15% = [76.5, 103.5] Ohm
100 Ohm +/-15% = [85, 115] Ohm
It seems the consensus is on 100 Ohm +/-15% for the differential impedance.
Toradex mentions something else which helps with the selection of
design parameters: "The differential impedance is always smaller than
twice the single-ended impedance"
Z(differential) < 2 * Z(single-ended)[14]
=> Z(single-ended) > Z(differential) / 2
Thus, if we wish to have Z(differential) = 100 Ohm +/-15%, we should
choose the single-ended impedance such that
Z(single-ended) > (100 Ohm +/-15%) / 2 = 50 Ohm +/-7.5%
Toradex suggests 55 Ohm single-ended impedance to coincide with 100
Ohm differential impedance.[15]
In order to model and calculate expected impedance we need to describe
the geometry of the arrangement of traces, reference planes, and
dielectric layers in the PCB.
PCB Dimensions (not drawn to scale or even to correct aspect ratio):
______
^
T (thickness of copper in signal layer)
v
_______________________________
^
H (thickness or height of insulator)
v
_______________________________
reference plane (GND or Power)
_______________________________
The 6-layer FR-4 PCB chosen for EOMA68-A20 has the following
characteristic dimensions:
total thickness of PCB = 1.2mm ~= 47.3mil
H(height of dielectric between outer copper layer and adjacent
reference plane) = 6.4mil
copper cladding = 1oz
min{W(trace width)} = 5mil
min{S(trace-to-trace space)} = 5mil
min{diameter(plated through-hole vias)} = 6mil
diameter(via surround/pad) = 12mil
To calculate the thickness (T) of 1 ounce copper requires several
conversion factors and the density of copper. "1 ounce copper" refers
to the thickness of 1 ounce (avoirdupois versus troy) of copper spread
over 1 square foot. There is at least one web site which purports to
calculate the thickness in mils of a particular weight of copper
cladding[16], but they use some pretty heavy approximations for
otherwise well-known conversion factors and conclude that 1.37 mil = 1
oz Cu. I used the standard unit conversion factors as shown below:
Given:
Areal density = 1 oz Cu / ft^2
Exact conversion factors:
1 (avoirdupois) oz = 28.349523125g [17]
1 ft^2 = (1ft * 12in/1ft * 2.54cm/1in)^2 = (30.48cm)^2
Empirical value:
Density (Cu pure) rho = 8.96 g / cm^3 [18][19: CRC, LNG]
Calculation:
T = areal density(given) * conversion(oz->g) / (volume density) /
conversion(ft->cm)^2[16]
T = 1 oz Cu / ft^2 * 28.349523125g / 1 oz * 1 cm^3 Cu / 8.96 g Cu * 1
ft^2 / (30.48cm)^2
= 0.003405711cm Cu = 0.03405711mm * 1in / 25.4mm * 1000mil / 1in = 1.34mil Cu
(Using 8.92 gCu / cm^3 [19: WEL] => T = 1.35mil Cu)
The most well-attested value for copper's density was 8.96 g/cm^3
yielding T = 1.34mil Cu. Illustrating the sensitivity of the
calculation to variation of parameters, the minority density value of
8.92 g/cm^3 yielded T = 1.35mil Cu.
Microstrip PCB Dimensions (not drawn to scale or even to correct aspect ratio):
<-W-><--- S ---><-W-><----- D ----->
__IIIII___________IIIII___________________IIIII
Signal:+ - x
W = design width of trace
S = spacing between traces of differential pair (+,-)
D = spacing to unrelated signal "x" (another pair, ground shield, etc.)
Texas Instruments gives some equations to help calculate trace
geometries for 100 Ohm differential impedance.[12]
Z(differential) = 2 * Z(single-ended) * (1 - 0.48 * exp(-0.96 * S / H))
Z(single-ended) = 88.75/sqrt(relative permittivity + 1.47) * ln(5.97 *
H / (0.8 * W + T))
Since the board material and manufacturing process specify the parameters:
relative permittivity(FR-4) = 4.4[1]
H = 6.4mil
T = 1.34mil
and the HDMI standard specifies:
Z(differential) = 100 Ohm
we have two equations in three unknowns:
Z(single-ended), W, S
Given the guidance that Z(single-ended) > 50 Ohm, we can solve the
second equation for W(Z(single-ended)),
W<mils> = 7.463 * H * exp(-Z(single-ended) * sqrt(relative
permittivity + 1.47) / 88.75) -1.25 * T
Then select a value for Z(single-ended), turn the crank and see what
value of W we come up with. After looking at the result we may decide
to select a different value for Z(single-ended) and calculate the
concomitant W in order to find a routable trace width and a usable
single-ended impedance.
Let's try this for Z(single-ended) = 55 Ohm.
W(Z(single-ended) = 55 Ohm) = 7.463 * 6.4mil * exp (-55 Ohm * sqrt(4.4
+ 1.47)/88.75) - 1.25 * 1.34mil
= 8.97mil
Then we can solve the equation that gives differential impedance for
S, plug in our values for single-ended and differential impedance and
see what trace-spacing (S) we get.
S = -H / 0.96 * ln((2 * Z(single-ended) - Z(differential)) / 0.96 /
Z(single-ended))
S(Z(single-ended) = 55 Ohm) = -6.4mil / 0.96 * ln((2 * 55 Ohm - 100
Ohm) / 0.96 / 55 Ohm)
= 11.1mil
The distance, D, to adjacent signal pairs and shield traces is suggested to be,
D >= 3 * S[12]
with the caveat that running a ground shield trace on only one side
can create an imbalance that increases EMI. "Ground trace shields
should have a scattering of vias to the underlying ground plane."[12]
Z(single-ended) W<mil> S<mil> min{D}<mil>
<Ohm>
51 10.2 21.3 63.9
55 8.97 11.1 33.3
60.1 7.58 7.00 21.0
64.6 6.51 5.02 15.1
Table of single-ended impedances and associated trace width and
spacing.[These numbers are based on formulas which are approximations
with error bounds of +/-10%.][12]
Here we can see the effect of changing the single-ended impedance on
width and spacing of traces in a differential pair of given
differential impedance. By raising the single-ended impedance we
reduced both the width of the traces and also the spacing. The other
outgrowth is that the common-mode rejection is improved by lowering
the single-ended impedance of the traces. Common-mode signal stems
from other signals (EMI) coupled into the traces, uncompensated
intra-pair skew, and imperfect differential signal drivers at the
source. Common-mode signal will radiate (EMI) from circuit board
traces. So we have a trade-off to consider:
1. We can minimize common-mode signal by lowering single-ended
impedance which increases the trace width and spacing for a given
differential impedance.
2. This is limited by the fact that, for a microstrip differential
pair, the single-ended impedance is greater than half the differential
impedance.
Looking at the single-ended impedance values, the difference between
51 Ohm and 64.6 Ohm is an increase of less than 30% and thus won't
drastically change the common-mode performance, so my inclination if
you're strapped for space would be to use the higher single-ended
impedance with 6.5mil wide traces spaced apart 5mils and try for
15mils between pairs.
Reviewing with reference to TI's "Routing Guidelines"[20]:
i. Use the smallest trace spacing possible, which usually is
specified by your PCB vendor: in our case 5 mils
ii. Make sure the geometries obey:
a. S < H; (S = 5mil) < (H = 6.4mil)
b. S < W; (S = 5mil) < (W = 6.5mil)
c. W < 2H; (W = 6.5mil) < (2H = 12.8mil)
d. D > 2S = 10mil
Looks like we abide by their guidelines if we use the 64.6 Ohm
single-ended impedance values. It seems the distance, D, to the next
trace is somewhat flexible because in this reference it is reduced
from 3S to 2S. (I'm sure 3S is better than 2S, if you have the
space.)
Ground Planes under Pads
Toradex mentions the lower impedance between wide traces and the
reference plane causing impedance mismatch at large pads for
components and connectors.[21] The width of the pads in the
illustration are 5-6x the width of the traces connecting to them. On
the micro-HDMI connector the width of the pads is around 0.2mm (JAE
DC3R019JA7R1500 pad width = 0.23 +/-0.03 mm ~= 9.1 +/- 1.1 mil), where
the smallest trace we can have is 5 mil thus our greatest proportion
is 10.2 mil / 5 mil ~ 2. So this is probably less of a problem than
if the pads were 5-6 times the width of our traces. In fact if we
compare the dimensions of the connector pads and spacing (which is
about the same as pad width) to those of the trace width and spacing
for 55 Ohm single-ended impedance in the table above, they nearly
match. Thus I don't think this will be a big issue for this board
because while the pads are wider than our traces, they're spaced about
as far apart as we would space traces that are that wide to still get
100 Ohm differential impedance.
Via Impedance
If and when we start supporting HDMI v2.0+ we will need to tune the
impedance of our signal vias even more keenly as our signals will
surpass the 10GHz barrier.[22] Presently we also have the happy
situation that since our high-frequency signal vias always connect
between top and bottom layers, our stub length is 0 on signal vias.
Creating transparent (tuned) vias requires familiarity with a 3-D EM
simulator and some time to set up, run, evaluate results of
simulations, and then repeat in order to tune the impedance. (See
section below "Libre Field Solvers".)
We can still take some of the recommendations to heart:
1. Use minimal size vias for high-frequency traces to reduce
parasitic capacitance.[23]
2. Place the two vias of the differential pair in close proximity to
increase capacitive coupling between the signals.(smaller via pitch)
3. Instead of using two separate anti-pads on signal vias, combine
them into oval shared antipads (on every layer) to reduce parasitic
capacitance.
4. Place ground vias next to signal vias to provide ground-return
paths.[22, Figure 2]
References:
[1] https://en.wikipedia.org/wiki/FR-4
[2] Toradex, page 21
[3] Toradex, page 38
[4] TI, page 4
[5] Chrontel, page 5
[6] https://forum.allaboutcircuits.com/threads/hdmi-inter-intra-pair-skew-inter-pair-synchronization.75801/
[7] https://e2e.ti.com/support/interface/high_speed_interface/f/138/t/267205
[8] https://www.researchgate.net/publication/224650488_Effects_of_skew_on_EMI_for_HDMI_connectors_and_cables
[9] Toradex, page 17, Figures 12 & 13
[10] Toradex, pages 22-23
[11] Chrontel, page 4
[12] TI, page 5
[13] JAE, page 1
[14] Toradex, page 12
[15] Toradex, page 13, Table 3
[16] http://referencedesigner.com/cal/cal_02.php
[17] https://en.wikipedia.org/wiki/Ounce#International_avoirdupois_ounce
[18] https://en.wikipedia.org/wiki/Copper
[19] https://en.wikipedia.org/wiki/Densities_of_the_elements_(data_page)
[20] TI, page 8
[21] Toradex, pages 18-19, Figure 16
[22] https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs-four-things-you-need-to-know-about-vias
[23] TI, page 9
Bibliography:
Chrontel: Application Note AN-B026, "PCB Layout and Design Guide for
CH7101A HDMI to VGA Converter",
http://www.chrontel.com/media/Application%20Notes/AN-B026%20Rev0.2.pdf
Japan Aviation Electronics Industry, Ltd. (JAE): "HDMI Standard Type
D HDMI Micro Connector: DC3 Series", Connector MB-0233-2, May 2013,
http://www.jae.com/z-en/pdf_download_exec.cfm?param=MB-0233-2E_DC3.pdf
Texas Instruments (TI): "HDMI Design Guide", High-Speed Interface
Products, June 2007,
http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-138-01-00-00-10-65-80/Texas-Instruments-HDMI-Design-Guide.pdf
Toradex: "Layout Design Guide", v1.0, 14 April 2015,
http://docs.toradex.com/102492-layout-design-guide.pdf
_______________________________________________
arm-netbook mailing list arm-***@lists.phcomp.co.uk
http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook
Send large attachmen
