[Arm-netbook] HDMI High-Frequency Layout: Recommendations

[Richard Wilbur]

HDMI Layout Notes
for EOMA68 Cards
by Richard Wilbur
Thu 3 Aug 2017

Recommendations for this Layout

Source (processor) end:

Could we shrink the via pitch between constituents of a differential
pair (bring the vias of a differential pair closer to each other) and
combine the anti-pads into an oval shape on each layer? This reduces
fringing fields and thus parasitic capacitance.

I like the ground vias close to the signal vias between differential
pairs. It would be lovely to get a ground via close to the via on
HTX2P and possibly move the one between HTX2N and HTX1P closer to the
signal vias (if the signal vias of pairs can be moved closer with
combining the anti-pads).

What is the intra-pair skew from the processor lands to the first
signal vias? I wonder if we could move the vias on the short lines a
little further from the processor and make up some of the skew in that
segment before we leave it?

Sink (connector) end:

Same thing for differential pair vias--HTX0 and HTX2--it would be
lovely to shrink the via pitch and combine anti-pads (if possible).
Again, I like the ground vias close to the signal vias HTX2P, HTX2N,
and HTX0P. It would be lovely to be able to either put a new ground
via closer to the signal via on HTX0N or move the one on the ground
shield trace closer.

I like what you were showing on the video with the signal vias at the
connector lands: putting a neck on the trace between the via and the
land should dampen the spirits of the solder but not the signals.

If we could reduce the signal via pitch by combining anti-pads at the
connector, we might be able to move the HTX1P and HTXCN signal vias to
the other side of the lands next to the other side of the differential
pair, thus equalizing the skew on the segment between the ESD chip
pads and the connector pads. If that worked the final touch might be
to add a ground via between DC3 pin 10 (GND) and the board edge for
return current paths.

Other than that, I would try and move as much of the skew compensation
close to the source of the skew as possible.

I'm not sure what I'm looking at as you mentioned the ground reference
planes were solid under the HDMI differential pairs, but it looks like
they have voids under the signals in the pictures. Am I seeing a
negative, that there are only little strips of conductor in the ground
reference plane directly under the high-frequency lines? Neither of
these interpretations is very satisfactory, nor do they seem to
represent reality.

Please let me know what can and can't be done and I will adjust
recommendations accordingly.

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[Luke Kenneth Casson Leighton]

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Post by Richard Wilbur
HDMI Layout Notes
for EOMA68 Cards
by Richard Wilbur
Thu 3 Aug 2017
Recommendations for this Layout
Could we shrink the via pitch between constituents of a differential
pair (bring the vias of a differential pair closer to each other)

maaayyybeee? PADS does the distances automatically, so it would
involve manual editing (and second-guessing of the automated rules /
best-practices for diff-pair routing in PADS)

Post by Richard Wilbur
and
combine the anti-pads into an oval shape on each layer? This reduces
fringing fields and thus parasitic capacitance.

https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs-four-things-you-need-to-know-about-vias

ok found it... hmmmm yeah i can see how that would work.

ok see attached little image: turns out that the GND copper
flood-fill clearance is enough to *automatically* create the
equivalent of what you're referring to.

Post by Richard Wilbur
I like the ground vias close to the signal vias between differential
pairs. It would be lovely to get a ground via close to the via on
HTX2P and possibly move the one between HTX2N and HTX1P closer to the
signal vias (if the signal vias of pairs can be moved closer with
combining the anti-pads).

yeah i think i can do the one on HTX2P... but it involves: *deep breath*

moving HSCL and all those other signals further over

inverting the XTAL-IN and XTAL-OUT signals so that one of them goes
the *other* side of its BGA pad

moving and re-routing the PWM and EINT-0 signals (which are too close
anyway) with those vias, to the XTAL signals

possibly routing HSDA round the *back*... no that takes it past the
diffpairs... HHPD routing *right* instead of down... that would be
okay.... it would go past the USB diff-pairs though.... i think i can
tolerate that..

Post by Richard Wilbur
What is the intra-pair skew from the processor lands to the first
signal vias? I wonder if we could move the vias on the short lines a
little further from the processor and make up some of the skew in that
segment before we leave it?

yes i was considering that - maybe just staggering the vias so for
example HXTX1N and P are inverted as to how they really should be.

Post by Richard Wilbur
Same thing for differential pair vias--HTX0 and HTX2--it would be
lovely to shrink the via pitch and combine anti-pads (if possible).
Again, I like the ground vias close to the signal vias HTX2P, HTX2N,
and HTX0P. It would be lovely to be able to either put a new ground
via closer to the signal via on HTX0N or move the one on the ground
shield trace closer.

it's virtually impossible to get anything in there, because of the
three Rclamp0524p components (anti-static protection).

i'm going to move one of the rclamp0524p's so that it's directly
above the other, and it *might* then be possible to fit some GND vias
in there.

also i realised that the path is shorter to the DC3 connector because
of the via staggering, so i will have to put a small "wiggle" into the
shorter path right at that point. why? because the signals should be
properly matched right up to that point.

Post by Richard Wilbur
I like what you were showing on the video with the signal vias at the
connector lands: putting a neck on the trace between the via and the
land should dampen the spirits of the solder but not the signals.

yehyeh.

Post by Richard Wilbur
If we could reduce the signal via pitch by combining anti-pads at the
connector, we might be able to move the HTX1P and HTXCN signal vias to
the other side of the lands next to the other side of the differential
pair, thus equalizing the skew on the segment between the ESD chip
pads and the connector pads.

yehyeh i get it.

nomnomnom....

it might just be doable. i'd have to shrink the size of the two GND
pads, 16 and 4, then the vias for 14 and 6 could be moved to the other
side then *diagonal* (right).... shrinking the size of 10 as well
would allow the existing vias to the right of 8 and 12 to *also* be
moved diagonally to the right... changing them to 0302s would give
some extra clearance, it's risky but what about this isn't...

Post by Richard Wilbur
If that worked the final touch might be
to add a ground via between DC3 pin 10 (GND) and the board edge for
return current paths.
Other than that, I would try and move as much of the skew compensation
close to the source of the skew as possible.

yehyeh *sigh* i missed that. frack. gonna have to redo the whole
frackin lot, one path at a time, so i can make sure each segment is
matched. frack!!

Post by Richard Wilbur
I'm not sure what I'm looking at as you mentioned the ground reference
planes were solid under the HDMI differential pairs,

yes.

Post by Richard Wilbur
but it looks like
they have voids under the signals in the pictures.

no,

Post by Richard Wilbur
Am I seeing a negative,

you're seeing the board pre-flood. when flooding is done it f***s
things up in PADS, causes it to be very unstable (especially if you
switch it to "invisible" with SPO and PO / PD keystroke commands).
also massively increases the file size. also gets in the way as you
can't see a damn thing.

also if it was a real-time feature the entire system would grind to a
halt as it takes about ten SECONDS to recalculate the flood-fill.

and yes layers 2 and 5 are solid GND planes.

Post by Richard Wilbur
that there are only little strips of conductor in the ground
reference plane directly under the high-frequency lines? Neither of
these interpretations is very satisfactory, nor do they seem to
represent reality.

you may be referring to the little ground tracks i added. these are
there because the copper-to-everything-else clearance i set to
around.... i think... 7 or perhaps 10mil, so that it doesn't get
absolutely everywhere.

however i *want* the GND plane (on 1) to go into nooks and
crannies.... reach the parts that other beers can't reach... only way
to do that is manually.

Post by Richard Wilbur
Please let me know what can and can't be done and I will adjust
recommendations accordingly.

appreciated.

well, let me try the DC3 experiment of moving the VIAs to the other
side. that i feel is really important.

l.
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[Luke Kenneth Casson Leighton]

it works! signals on layer 6 (blue) can be made properly diff-paired.
only concern: both vias are now right hard-up against the board edge.
but... again, their pins are directly above them, and they're leading
into the metal case which is entirely shielded. so i *think* it's ok.

l.
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[Richard Wilbur]

Sent from my iPhone

Post by Luke Kenneth Casson Leighton
it works! signals on layer 6 (blue) can be made properly diff-paired.
only concern: both vias are now right hard-up against the board edge.
but... again, their pins are directly above them, and they're leading
into the metal case which is entirely shielded. so i *think* it's ok.

I agree as this is a mid-mount connector with metal body/shield, right? The metal extends down covering the board edge, doesn't it?

Sounds like a pretty cool accomplishment. It probably looks nice, too! That's one of things I've noticed, a good design tends to have an appealing appearance.
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Post by Richard Wilbur
Sent from my iPhone

Post by Luke Kenneth Casson Leighton
it works! signals on layer 6 (blue) can be made properly diff-paired.
only concern: both vias are now right hard-up against the board edge.
but... again, their pins are directly above them, and they're leading
into the metal case which is entirely shielded. so i *think* it's ok.

I agree as this is a mid-mount connector with metal body/shield, right?

yehyeh... but in one sample it had some sort of thing coming down to
meet the board, but in the reel of 1500 they don't.

Post by Richard Wilbur
The metal extends down covering the board edge, doesn't it?

top and bottom (horizontally) yes, but vertically, no.

Post by Richard Wilbur
Sounds like a pretty cool accomplishment.

well i wouldn't have tried it if you hadn't pushed me

Post by Richard Wilbur
It probably looks nice, too!

it does.

Post by Richard Wilbur
That's one of things I've noticed, a good design tends to have an appealing appearance.

ah gooood. someone else who noticed that beauty and elegance seems
to actually.... work.

l.

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[Luke Kenneth Casson Leighton]

okaay, so this is what i've managed for the outgoing vias (layer 1),
the two lengths are equal (to each other and including across all four
pairs) and the relative positions of each via are identical.

for layer 6.... faak it's tight on space down the bottom, so i simply
can't get anything but "turns" in. it'll have to go dead-straight
until the other end of the board, after the PMIC, where i'll then be
able to correct the length differences between the CLK pair and the
other pairs.

richard you said that the difference between all pairs should be no
more than 100mil, right? but that clock should be a leetle bit
longer.

CLK-pairs are 57.245 (i got them to within a thousandth of a mm!
57.245 and 57.24518 how jammy is that!!)

HX2N/P are 49.something - a hell of a big difference. luckily that
one's on the outside edge so i can "wiggle" it a lot :)

oh... i had another go at the USB pairs, after reading all that you
recommended i wasn't happy that there was skew (which i never noticed
before). the USB lines worked but there would have been quite a bit
of EM.

l.

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... forgot the images...
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Post by Luke Kenneth Casson Leighton
... forgot the images...

No image's here on the list

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Post by Luke Kenneth Casson Leighton
... forgot the images...

No image's here on the list

argh. bletch. frick. arse.

damnit that'll be because i enabled attachment-stripping, didn't
i.... *sigh* :)

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[Luke Kenneth Casson Leighton]

next set...

wiggles.jpg is the layer 6 length-matching area: HX2N/P is the one
that's the longest, it snakes back on itself. i length-matched all 3
signal pairs to 56.413, and left the CK lines at 57.134 just to give
the tiniest bit of delay (TI recommendations iirc).

no - not even enough space to do 5.1mil / 5.0 clearance... just... too much.

the other images show the via'd portions, they're all either
symmetrical or perfectly length-matched to 0.001mm.

l.

[m***@gmail.com]

Post by Luke Kenneth Casson Leighton
next set...

GND shielding parallel to the differentials is interrupted quite
often. Those GND tracks act as shields, for emission and reception.
I'd try to put as much parallel GND as possible.

And trace the parallel GND around the via's, see attachment.

Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.

Also I'd personally not use curved wriggles. HF signals travel in a
straight direction. With curves they start diffracting and start
bouncing cross each other and might start to radiate or echo back. But
I see that the community is divided on that stance.

If tight for space you can use 90% corners with a chamfered outer
edge. I suppose the chamfer acts like a mirror.

https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100
Figure 6

[Hrvoje Lasic]

the case for GND around differential pairs cant hurt, maybe even can help.
But is it better to have GND in plane below that actually is doing same
things? If there is no clear path for signal to go back then I guess put
GND in parallel is good but if you have clean GND below than make it
somehow redundant. Or am I wrong? I am discussing these because most
probably there is tight space even without GND lines...

Post by m***@gmail.com

Post by Luke Kenneth Casson Leighton
next set...

GND shielding parallel to the differentials is interrupted quite
often. Those GND tracks act as shields, for emission and reception.
I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.
Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.
Also I'd personally not use curved wriggles. HF signals travel in a
straight direction. With curves they start diffracting and start
bouncing cross each other and might start to radiate or echo back. But
I see that the community is divided on that stance.
If tight for space you can use 90% corners with a chamfered outer
edge. I suppose the chamfer acts like a mirror.

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Post by Hrvoje Lasic
the case for GND around differential pairs cant hurt, maybe even can help.
But is it better to have GND in plane below that actually is doing same
things? If there is no clear path for signal to go back then I guess put
GND in parallel is good but if you have clean GND below than make it
somehow redundant. Or am I wrong? I am discussing these because most
probably there is tight space even without GND lines...

the most amazing borad i saw was a 2-layer 5-port GbE router. man
you should have seen the diff-pairs on that. it was... beautiful.
every ethernet diffpair - bear in mind this is GbE with 5 ports - so
that's TWENTY pairs - had GND vias equally spaced an absolute specific
distance from them, absolutely regularly like clockwork every couple
of mm.

what that does is make *absolutely* certain that there's no
cross-talk between the diff-pairs. with only a 5 mil GND trace
between pairs i am really pushing it, but there really isn't any
choice here.

the first design (done by a superb senior engineer at wits-tech)
didn't even have the GND separation between diff-pairs, and yet
amazingly it worked. i don't feel comfortable leaving them out, but i
can't get vias in at both ends on all pairs.

l.

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Post by Luke Kenneth Casson Leighton
next set...

GND shielding parallel to the differentials is interrupted quite
often.

because there's simply not enough space to do otherwise. if i could
move the entire CPU and RAM up another 0.5mm it would be doable. but
then i would have to re-route 12 signals which go around the top area
of the board and that's (a) risky and (b) not enough space to do it.

Post by m***@gmail.com
Those GND tracks act as shields, for emission and reception.
I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.

ah, got it - thanks for the tip, i thought i'd done that on all
diffpairs, but i missed one. good call.

yes there's only one, because the layer 1 and layer 6 will be
flood-filled and that will fill the areas that "appear" to be missed.

Post by m***@gmail.com
Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.

these are layer 1 and layer 6, and layer 2 and 5 are solid GND.

Post by m***@gmail.com
Also I'd personally not use curved wriggles. HF signals travel in a
straight direction. With curves they start diffracting and start
bouncing cross each other and might start to radiate or echo back.

mmmmm.... *stress*! anyone else feel the curves are "Bad"?

Post by m***@gmail.com
But
I see that the community is divided on that stance.
If tight for space you can use 90% corners with a chamfered outer
edge. I suppose the chamfer acts like a mirror.

i'd *really* prefer not to do that :)

Post by m***@gmail.com
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100
Figure 6

wow that's pretty bad-ass.

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Post by Luke Kenneth Casson Leighton

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Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.

these are layer 1 and layer 6, and layer 2 and 5 are solid GND.

I was referring mostly to layer 3 and 4. The diff pair is either on 3
or 4. If it is on 3 a slab of GND should be on 4 and vice versa.

It's
1. Vsuply + components
2. Ground
3. HF
4. HF
5. Ground
6. Vsuply + componnents

Right?

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
If tight for space you can use 90% corners with a chamfered outer
edge. I suppose the chamfer acts like a mirror.

i'd *really* prefer not to do that :)

Post by m***@gmail.com
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100
Figure 6

wow that's pretty bad-ass.

Yeah I had read a more extensive guide in a TI pdf somewhere, can find
it at the moment. But TI documentation also schizo's on curves vs.
corners of 35 degrees and chamfered 90 degrees.

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Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.

these are layer 1 and layer 6, and layer 2 and 5 are solid GND.

I was referring mostly to layer 3 and 4. The diff pair is either on 3
or 4.

no.

Post by m***@gmail.com
If it is on 3 a slab of GND should be on 4 and vice versa.
It's
1. Vsuply + components
2. Ground
3. HF
4. HF
5. Ground
6. Vsuply + componnents
Right?

no.

1. SIG1 + components
2. Ground
3. SIG3
4. POWR
5. Ground
6. SIG6 + componnents

there's only 3 signal layers: 1, 3 and 6. there are NO HDMI
diffpairs on layer 3. i'm not happy about the fact that i have to use
vias *at all* but there's no choice: layer 1 the 24mhz XTAL and the
PMIC are in the way, and when you get to the DC3 connector the signals
*have* to go round the back (layer 6) anyway.

l.

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Post by Luke Kenneth Casson Leighton
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Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.

these are layer 1 and layer 6, and layer 2 and 5 are solid GND.

I was referring mostly to layer 3 and 4. The diff pair is either on 3
or 4.

no.

Post by m***@gmail.com
If it is on 3 a slab of GND should be on 4 and vice versa.
It's
1. Vsuply + components
2. Ground
3. HF
4. HF
5. Ground
6. Vsuply + componnents
Right?

no.
1. SIG1 + components
2. Ground
3. SIG3
4. POWR
5. Ground
6. SIG6 + componnents

this is what we have been using for our design more or less and that came
with freescale reference design as well.

Post by Luke Kenneth Casson Leighton
there's only 3 signal layers: 1, 3 and 6. there are NO HDMI
diffpairs on layer 3. i'm not happy about the fact that i have to use
vias *at all* but there's no choice: layer 1 the 24mhz XTAL and the
PMIC are in the way, and when you get to the DC3 connector the signals
*have* to go round the back (layer 6) anyway.
l.

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Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.

1. SIG1 + components
2. Ground
3. SIG3
4. POWR
5. Ground
6. SIG6 + componnents

That work's as well. But the enclosure should shield very well. And
there should not be a HF signals on layer 3.

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Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.

1. SIG1 + components
2. Ground
3. SIG3
4. POWR
5. Ground
6. SIG6 + componnents

That work's as well. But the enclosure should shield very well.

metal case... yes.

Post by m***@gmail.com
And
there should not be a HF signals on layer 3.

USB in places but not HDMI.

l.

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Post by Luke Kenneth Casson Leighton

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Post by Luke Kenneth Casson Leighton
next set...

GND shielding parallel to the differentials is interrupted quite
often.

because there's simply not enough space to do otherwise. if i could
move the entire CPU and RAM up another 0.5mm it would be doable. but
then i would have to re-route 12 signals which go around the top area
of the board and that's (a) risky and (b) not enough space to do it.

I found quite some room. See attachments. Red: Easy improvement.
Yellow questionable but could use some improvement. Excuse the crappy
image editor it's all I have at the moment.

Also wouldn't a GND infill on the signal layers be preferable? As log
not unconnected islands emerge.

[Luke Kenneth Casson Leighton]

Post by m***@gmail.com
I found quite some room. See attachments. Red: Easy improvement.

yep, all those will be covered by flood-fill: no need to do them
manually. wiggles3_mv, the HXT0 and HXT1 GND segment on the left
middle, that one i got.

but near IPSOUT, top left, in wiggles_mv? no. it means moving those
IPSOUT vias, and i'm not doing that. am i. can i yes. am i going
to... mmmmm..... *strains*.... okayokay you twisted my arm :)

Post by m***@gmail.com
Yellow questionable but could use some improvement. Excuse the crappy
image editor it's all I have at the moment.

i _like_ crappy editors, i use them all the time :) as long as it
gets the job done and it doesn't take long, communicates the intent,
*why* would you spend $600 and hours of time?? :)

Post by m***@gmail.com
Also wouldn't a GND infill on the signal layers be preferable? As log
not unconnected islands emerge.

GND infill *is* going to be done on the signal layers. but the
copper-to-track clearance is 10mil (where tracks are 5mil). so what
happens is: any space smaller than 10mil does *not* get flood-filled.
so i put little "leaders" - like you can see - into the areas where
the beer cannot reach.

l.

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Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Also wouldn't a GND infill on the signal layers be preferable? As log
not unconnected islands emerge.

GND infill *is* going to be done on the signal layers. but the
copper-to-track clearance is 10mil (where tracks are 5mil). so what
happens is: any space smaller than 10mil does *not* get flood-filled.
so i put little "leaders" - like you can see - into the areas where
the beer cannot reach.

Ah that explains a lot indeed. Too bad the infill isn't visualized.

Sadly the space between the HDMI connectors is to small to fill. That
would encapsulate the HDMI signal pairs.

Post by Luke Kenneth Casson Leighton
http://youtu.be/ab6dJYDgj48

LOL

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Post by m***@gmail.com
Ah that explains a lot indeed. Too bad the infill isn't visualized.

i can do a flood-fill and screenshot the gerber files, i'll do that
for a final check.

Post by m***@gmail.com
Sadly the space between the HDMI connectors is to small to fill. That
would encapsulate the HDMI signal pairs.

that's why, if you look carefully, each pair has a GND pad directly
opposite it. this is by design in the MicroHDMI connector
specification, it's *designed* to be 10 / 9 staggered pins.

l.

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Post by m***@gmail.com
GND shielding parallel to the differentials is interrupted quite
often. Those GND tracks act as shields, for emission and reception.
I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.
Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.
Also I'd personally not use curved wriggles. HF signals travel in a
straight direction. With curves they start diffracting and start
bouncing cross each other and might start to radiate or echo back. But
I see that the community is divided on that stance.

I also prefer 45 degree corners to the curves. Looks like they only
occur in one section.

Post by m***@gmail.com
If tight for space you can use 90% corners with a chamfered outer
edge. I suppose the chamfer acts like a mirror.
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100
Figure 6

This is good advice for single-ended signals on a
stripline--high-speed digital and RF. That is the situation Maxim are
addressing in the referenced document. The signals we are dealing
with are high-speed digital but transmitted in differential mode on a
microstrip.

Single-ended signals are transmitted relative to a ground reference
and so putting ground reference next to them tends to block the
side-view of the antenna created by either microstrip or stripline,
thus reducing radiated and coupled interference. That's a very good
thing!

microstrip (The following diagrams are in cross-section perpendicular
to the direction of signal transmission. Think of the signal going
into the diagram away from the viewer.)

single-ended signal without ground shield traces

signal +
dielectric from the side we see a dipole antenna
ground -

single-ended signal with ground shield traces
- + -
ground signal ground -
dielectric dielectrc dielectric
ground ground ground ground -

(ground shield traces would need some vias to connect them with ground
plane) This blocks the view of the dipole antenna from the side and
reduces the size of the dipole antenna so that far field it is
vanishingly small being primarily the area between the ground shield
traces and the signal trace. (Far field: distance from microstrip at
least 10 * separation between signal and ground shield traces.)

Since we have a different geometry, the problem changes. We are using
differential microstrips. Differential-mode signals are transmitted
relative to each other instead of ground. Only common-mode noise in
the signals is transmitted relative to ground.

microstrip

differential-mode signal without ground shield traces

signal+ signal-
dielectric dielectric
ground ground ground

Here the dipole antenna is limited to area between the two signal
traces, blocked on the bottom side by ground plane, and insignificant
in far field (because the traces are close together, have opposite
potential and currents, and the fields cancel each other).

I'm out of time to add detail or references, so sending now.

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[Luke Kenneth Casson Leighton]

On Fri, Aug 11, 2017 at 6:15 PM, Richard Wilbur

Post by Richard Wilbur

Post by m***@gmail.com
Also I'd personally not use curved wriggles. HF signals travel in a
straight direction. With curves they start diffracting and start
bouncing cross each other and might start to radiate or echo back. But
I see that the community is divided on that stance.

I also prefer 45 degree corners to the curves. Looks like they only
occur in one section.

yes - i was trying to save space. ok i managed to get some 45-corner
wiggles in, instead. and also got the GND separation in between the
CK lines up to the via.

i'd *really* like to get this done and into test, particularly the
DC3 connector test PCB (first).

ok. so wiggles1.jpg is the beginning part. track-pairs remain
slightly offset, if you take the difference betweeen each pair it's
nearly... 8 mm because the clock lines have to go down (3mm) then
right-angle (2mm) then right (2mm) just to catch up with TX2.

so they _stay_ up to 8mm out until they get to the right end.. then
they wiggle again to get match-lengthed.

BUT... it just occurred to me that on the *other* side of those ESD
rclamp0524p protectors the diff-pairs are all *different lengths*.

so on the other side of the rclamp0524p components all four
diff-pairs will be different lengths.

would that be sufficient, do you think, richard, to satisfy the
"spread spectrum" style you were thinking of?

short lengths to the RIGHT of the rclamp0524p:

TXC: 3.11mm
TX0: 1.23mm
TX1: 3.23mm
TX2: 1.14mm

total lengths:

TXC:57.252mm
TX0:56.418mm
TX1:56.398mm
TX2: 56.401mm

so the signal pairs are all eever so slightly different, and they're
all around 0.85mm shorter than CK.

l.

[Luke Kenneth Casson Leighton]

btw yes i managed to move IPSOUT slightly to the right and got a GND
line in between them, without too much disruption. thank you for
prompting me to do that.

l.

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Post by Luke Kenneth Casson Leighton
btw yes i managed to move IPSOUT slightly to the right and got a GND
line in between them, without too much disruption. thank you for
prompting me to do that.

Amazing! Just a nitpick left. You mentioned the GND flood-fill
distance is 10mil. That means that GND will 10 mil removed from
tracks. Personally I'd trace the GND as close as possible to the diff
signals. But that may be just overcautious.

I don't have any fancy math like Richard so it might be FUD. Or just
my mild form of OCD. :-)

Or is that 10mil the minimum gap size? That would make sense.

Anyway a picture of the flood-fill will reveal everything.

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Post by m***@gmail.com

Post by Luke Kenneth Casson Leighton
btw yes i managed to move IPSOUT slightly to the right and got a GND
line in between them, without too much disruption. thank you for
prompting me to do that.

Amazing! Just a nitpick left. You mentioned the GND flood-fill
distance is 10mil. That means that GND will 10 mil removed from
tracks. Personally I'd trace the GND as close as possible to the diff
signals. But that may be just overcautious.

ok sorry, i was slightly wrong. clearance is also 5mil but there's
something called "rounding" on the flood fill which stops it from
curving into tight spaces.

Post by m***@gmail.com
I don't have any fancy math like Richard so it might be FUD. Or just
my mild form of OCD. :-)

:)

Post by m***@gmail.com
Or is that 10mil the minimum gap size? That would make sense.
Anyway a picture of the flood-fill will reveal everything.

attached. greyscaled (smaller). original GND tracks are still
visible but they're *combined* with the floodfill.

l.

[m***@gmail.com]

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Anyway a picture of the flood-fill will reveal everything.

attached. greyscaled (smaller). original GND tracks are still
visible but they're *combined* with the floodfill.

Looks pretty. Seeing that does raise a question too me. Is it
necessary to match length between the different pairs? I didn't think
that was a requirement. Because I see pairs wriggling and wasting a
lot of space.

I thought that only matching was required on a single pair. Impedance matching.

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Post by m***@gmail.com
Looks pretty. Seeing that does raise a question too me. Is it
necessary to match length between the different pairs? I didn't think
that was a requirement. Because I see pairs wriggling and wasting a
lot of space.
I thought that only matching was required on a single pair. Impedance matching.

that's what we've been discussing. read richard's message and my response.

l.

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Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Looks pretty. Seeing that does raise a question too me. Is it
necessary to match length between the different pairs? I didn't think
that was a requirement. Because I see pairs wriggling and wasting a
lot of space.
I thought that only matching was required on a single pair. Impedance matching.

that's what we've been discussing. read richard's message and my response.

I've read it again. But did not digest that from Richard's responses.

Inter-pair skew: Length (un)matching between two traces making op one
differential pair?

Intra-pair skew: Length (un)matching between differential pairs? Not mentioned.

What else I read so far:

Possibly remove the GND traces between pairs. Differential pairs are
designed to cancel each other out thus limit radiation. The pair
coupling creates force to repel incoming radiation noise. Correct me
if I'm wrong

The same construction as in twisted pair cables. But there you have
differential pair twisting creates an even bigger effect. But there we
also have types with shielding. Shielding around the whole set and
even with shielding per pair. The HMDI cables I've butchered had per
pair shielding and the other lines, clock, cec, etc, unshielded
bundled in one extra shield.

Removing the, intra pair, GND traces improves impedance, but decreases
shielding from external incoming radiation. But I suspect that effect
is limited due to the GND layer below, far bigger and nearer than
those traces.

Differential pairs should have a bigger, dielectric, space surrounding
them than they have to each other. Because the nearer you get to a
pair the less the differential cancelling effect. With the exception
for GND, which should act as a sink for EM emissions.

Removing the, intra pair, GND traces won't give you more space because
the pairs should keep the extra distance from each other.

Via's should occur only when, inter pair, length is matched.
Differential via's should have a rounded, oval, common, dielectric,
space surrounding them so the Z-axis radiation can cancel out
uninterrupted.

Digital differential signals might be skewed to begin with. Limiting
the differential EM canceling effect to begin with.

I'd say keep the intra pair GND traces. Maybe loose the intra pair
length mathing.

There should be no electric/magnetic coupling between intra pairs. But
if their length differs the parallel digital signals might become time
skewed. But I doubt that on this length that would be a problem.

Richards math should help with that along with max allowed digital
signal skew. Don't have the time to convert the math in a spreadsheet
calculator to confirm.

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Post by m***@gmail.com

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Looks pretty. Seeing that does raise a question too me. Is it
necessary to match length between the different pairs? I didn't think
that was a requirement. Because I see pairs wriggling and wasting a
lot of space.
I thought that only matching was required on a single pair. Impedance matching.

that's what we've been discussing. read richard's message and my response.

I've read it again. But did not digest that from Richard's responses.
Inter-pair skew: Length (un)matching between two traces making op one
differential pair?
Intra-pair skew: Length (un)matching between differential pairs? Not mentioned.

Ah it seems it's the other way around. Silly me. I knew why I kept
away from the intra and inter prefixes. I always switch them.

Post by m***@gmail.com
The HMDI cables I've butchered had per
pair shielding and the other lines, clock, cec, etc, unshielded
bundled in one extra shield.

Sorry. Clock is also one of the diff-pairs. As well as pin 17 and 19,
HEAC, Utilized for ARC (S/PDIF) and Ethernet. But not in the A20 so
less of a problem.

Post by m***@gmail.com
Richards math should help with that along with max allowed digital
signal skew. Don't have the time to convert the math in a spreadsheet
calculator to confirm.

Hmm not the only ones out there with these questions.

https://e2e.ti.com/support/interface/high_speed_interface/f/138/t/267205
"intra-pair length mismatch is recommended to be less than 5mils,
inter-pair length mismatch is less of a concern but the recommendation
is to keep the traces <2" and keep the clock slightly longer than the
data traces."

Keeping the clock longer makes sense. All the data is buffered before
the clock signal arrives.

https://forum.allaboutcircuits.com/threads/hdmi-inter-intra-pair-skew-inter-pair-synchronization.75801/
5bits of buffer.

http://ieeexplore.ieee.org/document/1706346/
https://www.researchgate.net/publication/224650488_Effects_of_skew_on_EMI_for_HDMI_connectors_and_cables
paywall, blegh. Put in a request on the second one. Let's see

https://www.infocomm.org/cps/rde/xbcr/infocomm/Dietro_HDMI.pdf
That explained the "eye diagrams". Overlapping differential signals.
Hmm 1bit buffer? 1920x1080p60 = 148.5 Mhz

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Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
I don't have any fancy math like Richard so it might be FUD. Or just
my mild form of OCD. :-)

:)

I'm sorry if any of this looks like fancy mathematics. (As someone whose first degree is in mathematics, I thought this was all very mundane algebra at best. I didn't get into field theory, Maxwell's equations [partial differential], et cetera.)

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Anyway a picture of the flood-fill will reveal everything.

attached. greyscaled (smaller). original GND tracks are still
visible but they're *combined* with the floodfill.

So I enjoyed looking at the picture but I'm curious what I'm looking at. Is this one layer? Which layer? What does the black mean? What about the gray?
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Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
I don't have any fancy math like Richard so it might be FUD. Or just
my mild form of OCD. :-)

:)

I'm sorry if any of this looks like fancy mathematics. (As someone whose first degree is in mathematics, I thought this was all very mundane algebra at best. I didn't get into field theory, Maxwell's equations [partial differential], et cetera.)

It is fancy math. And it is mundane. I didn't have the time refresh my
electrical formulas and/or follow yours. So it simply needs time and
attention.

Formulas don't teach you what's going on. It's
applying/verifying/quantifying your understaning of the subject. Any
one can apply simple formulas. But when you don't understand where
they come from you are just repeating tricks with the risk of doing it
wrong.

Your formulas are however infinitely more valuable then the fixed
recommendations but require more time to understand, verify and use:
http://www.ti.com/lit/an/spraar7g/spraar7g.pdf figure 13

That document has some nice recommendations.

I've been away from electrical calculations for 16 years now. So they
need time to enter my mind again and become applicable.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Anyway a picture of the flood-fill will reveal everything.

attached. greyscaled (smaller). original GND tracks are still
visible but they're *combined* with the floodfill.

So I enjoyed looking at the picture but I'm curious what I'm looking at. Is this one layer? Which layer? What does the black mean? What about the gray?

The normal traces are all in black. The GND fill is gray. If a trace
is GND the fill distance is 0 if not 5 thus connecting the GND traces
to the GND fill

Post by Richard Wilbur
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[Richard Wilbur]

I have some time today to continue this discussion.



Sent from my iPhone

Post by m***@gmail.com
GND shielding parallel to the differentials is interrupted quite
often. Those GND tracks act as shields, for emission and reception.
I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.
Make sure the'res as much solid GND on the layer above and below the
traces, again shielding.

microstrip

differential-mode signal with ground shield traces

ground signal+ signal- ground
dielectric dielectric dielectric dielectric
ground ground ground ground ground ground

Here the dipole antenna remains small and the half-strength fields between each signal trace and its associated ground guard shield trace work to truncate electric fields in the plane of the PCB. The fields are still insignificant in far field (because the traces are close together, have opposite potential and currents, and the fields cancel each other). It seems the best argument for including ground shield traces on this layout might be to guard against coupling signals between differential pairs that were packed in too closely to otherwise meet the recommended distance between different signal pairs. But with the dimensions of our layout being the minimum allowed by the board fabricator, the min(s) = min(w) => d = s + w + s = 3 * s.[1] So if we were to remove the ground shield traces from between differential pairs we could meet the inter-pair spacing recommendations without moving anything else. This may explain the design by the wits-tech senior engineer you mentioned which worked without ground shield traces between the differential pairs.

The ground shield traces surrounding a differential pair on the same layer will mostly block common-mode signal radiation and coupling. They will have little beneficial effect on differential signals--but can contribute asymmetric loading (lower single-ended impedance of one trace) to the differential pair (through asymmetric geometry) which will convert some differential energy into common-mode energy.

In other words, if we are expecting significant common-mode signal, whether from pathologies in the layout or incompetence of the differential-mode signal driver, then ground shield traces may be in order. Regardless, caveat emptor (let the buyer beware):
1. asymmetries in ground guard shield implementation contribute to conversion of differential signal to common-mode signal (which for a differential receiver is noise, thus lowering signal-to-noise ratio),
2. symmetric ground guard shield traces reduce the single-ended impedance of both traces of the differential pair, lowering the differential impedance of the pair. The effect is distance-dependent, the greater the spacing the less-pronounced the effect.

Another interesting reference on high-speed HDMI PCB layout is TI's SLLA324[2]. Notice how in none of the layouts pictured in Figures 4, 6, or 8 are there any ground shield traces. Judging from the eye diagrams in Figure 10, even with fairly close pair-to-pair spacing there doesn't seem to be significant cross-talk between the pairs (look for noise at transitions):
1. in the absence of ground shield traces
2. running at top speed of HDMI v1.4 (340MHz pixel clock, 1080p video, 3.4GHz data rate)
3. space between differential pairs doesn't seem to be all that large.

Figure 4 looks like it depicts a similar connector (micro HDMI <=> type D) and it looks like they have a similar pair length relationship (which, interestingly enough, they don't seem to take any pains to equalize):
length(D2) < length(D0) < length(D1) < length(CLK)

So, for the HDMI differential signals' sake, we don't necessarily need:
1. Ground guard traces between neighboring differential pairs
2. Ground guard traces between HDMI differential pairs and other circuits
3. Multiple ground vias riveting along the side of the board to block emissions
4. Perfectly matched inter-pair lengths

On the other hand:
1. Ground guard traces can be important in reducing noise radiated from single-ended circuits and coupled into other single-ended circuits on the board.
2. Ground fences, traces riveted with multiple ground vias, can help even more with the goals of "reducing noise radiated from and coupled into other single-ended circuits on the board" as above.

In other words, if we had more board space there are several things we could do differently: increase differential pair trace width and spacing, ground shield trace spacing.

But as it stands I believe it will likely work fine. Without changing anything else we could drop the ground shield traces which would serve to increase our differential impedance. We would want to retain the ground vias near signal vias.

Reference:
[1] HDMI, p. 5.2
[2] SLLA324, pp. 4-7

Bibliography:
Texas Instruments (TI): "HDMI Design Guide", High-Speed Interface
Products, June 2007,
http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-138-01-00-00-10-65-80/Texas-Instruments-HDMI-Design-Guide.pdf

Texas Instruments (TI): SLLA324 February 2012 Application Report, "TPD12S016 PCB Layout Guidelines for HDMI ESD"
http://www.ti.com/lit/an/slla324/slla324.pdf
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[Luke Kenneth Casson Leighton]

On Mon, Aug 14, 2017 at 10:37 PM, Richard Wilbur

Post by Richard Wilbur
I have some time today to continue this discussion.

awesome.

Post by Richard Wilbur
So if we were to remove the ground shield traces
from between differential pairs we could meet the
inter-pair spacing recommendations without moving
anything else. This may explain the design by the
wits-tech senior engineer you mentioned which worked
without ground shield traces between the differential pairs.

yehyeh. i could then move them slightly away from the edge of the board.

Post by Richard Wilbur
Another interesting reference on high-speed HDMI PCB layout is TI's SLLA324[2].

nnniiiiiice. i love it. that's exactly the same connector being
used. hmmm iinteresting, they bring the vias up from underneath on
all 4 diff-pairs...

Post by Richard Wilbur
1. Ground guard traces between neighboring differential pairs
2. Ground guard traces between HDMI differential pairs and other circuits
3. Multiple ground vias riveting along the side of the board to block emissions
4. Perfectly matched inter-pair lengths

hmmm....

Post by Richard Wilbur
1. Ground guard traces can be important in reducing noise radiated from single-ended circuits and coupled into other single-ended circuits on the board.
2. Ground fences, traces riveted with multiple ground vias, can help even more with the goals of "reducing noise radiated from and coupled into other single-ended circuits on the board" as above.
In other words, if we had more board space there are several things we could do differently: increase differential pair trace width and spacing, ground shield trace spacing.
But as it stands I believe it will likely work fine. Without changing anything else we could drop the ground shield traces which would serve to increase our differential impedance.

i think i will do that.

Post by Richard Wilbur
We would want to retain the ground vias near signal vias.

yehyeh.

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Post by Luke Kenneth Casson Leighton
On Mon, Aug 14, 2017 at 10:37 PM, Richard Wilbur

Post by Richard Wilbur
So if we were to remove the ground shield traces from between differential pairs we could meet the inter-pair spacing recommendations without moving anything else. This may explain the design by the wits-tech senior engineer you mentioned which worked without ground shield traces between the differential pairs.

yehyeh. i could then move them slightly away from the edge of the board.

I'm curious, what would you move? The goal of this was to get >= 15mil between any differential signal trace and any trace not from the same differential pair. The ground shield traces with 5mil spacing, 5mil trace width, and another 5mil spacing enforce this spacing on the differential signal traces. So if we remove the ground shield traces, and don't move anything closer, we get that spacing for previous effort.

Are you talking about moving the differential pairs further from the edge of the board? I'm guessing since there is a ground shield trace along the edge presently, that the ground shield trace would make the distance from the nearest differential trace to board edge at least s + w = 10mil. If the ground shield trace is 5mil from board edge then we have 15mil from nearest differential trace to board edge.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Another interesting reference on high-speed HDMI PCB layout is TI's SLLA324[2].

nnniiiiiice. i love it. that's exactly the same connector being
used. hmmm iinteresting, they bring the vias up from underneath on
all 4 diff-pairs...

I think that is to keep the path as similar for all 4 pairs as possible. Vias add delay and (if not properly tuned) reduce the impedance. So it seems they are working with the stratagem that it is better to treat each component of the signal the same.


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[Luke Kenneth Casson Leighton]

On Wed, Aug 16, 2017 at 6:11 AM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
yehyeh. i could then move them slightly away from the edge of the board.

I'm curious, what would you move? The goal of this was to get >=
15mil between any differential signal trace and any trace not
from the same differential pair.

ahhhh ok. i'm glad you're paying attention :)

Post by Richard Wilbur
The ground shield traces with 5mil spacing, 5mil trace width,
and another 5mil spacing enforce this spacing on the differential signal traces.
So if we remove the ground shield traces, and don't move anything closer,
we get that spacing for previous effort.

ha!

ok.

so.

if i just take *out* the ground intermediary traces that would do the
trick of bringing the impedance back up, is that right?

what would you suggest, here - leave the intermediary GND traces in
or take them out.

also, i think i "Get It" about the intermediary wiggles. when the
transmit end does automatic compensation that results in the signals
coming out in such a way that, really, the inter-pair length-matching
should be done from the *OPPOSITE* end i.e. from the CONNECTOR.

why?

because the automatic compensation will result in the signals coming
out with a small delay, which by the time they go round that big set
of bends they *WILL BE IN SYNC*.

ok they'll be in sync as long as all pairs are exactly the same
length from that point up until they meet the connector.

so the only bit that would be out-of-sync would be that huge set of
bends just after the transition from CPU-layer-1 onto layer 6, where
i've had to put in huge amounts of bend-compensation.

by adding in the down-stream inter-pair compensation just before the
rclamp0524p's) that *entire straight section* is out of sync... and
the set of bends is also out-of-sync so it's no improvement.

Post by Richard Wilbur
Are you talking about moving the differential pairs further
from the edge of the board?

yes. but from what you're saying it's not possible anyway.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Another interesting reference on high-speed HDMI PCB layout is TI's SLLA324[2].

nnniiiiiice. i love it. that's exactly the same connector being
used. hmmm iinteresting, they bring the vias up from underneath on
all 4 diff-pairs...

I think that is to keep the path as similar for all 4 pairs as possible.

yehyeh.

Post by Richard Wilbur
Vias add delay and (if not properly tuned) reduce the impedance.
So it seems they are working with the stratagem that it is
better to treat each component of the signal the same.

indeed. however i don't want to change the BOM, apart from anything
that's a TI part not a "Well Known Easily Sourceable Part In The Shenzhen
Huaqiang Road Eco-System".

dual rclamp0524's, one each side, it is.

l.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Wed, Aug 16, 2017 at 6:11 AM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
yehyeh. i could then move them slightly away from the edge of the board.

I'm curious, what would you move? The goal of this was to get >=
15mil between any differential signal trace and any trace not
from the same differential pair.

ahhhh ok. i'm glad you're paying attention :)

I'm trying ;>)

[…]

Post by Luke Kenneth Casson Leighton
if i just take *out* the ground intermediary traces that would do the
trick of bringing the impedance back up, is that right?

Should be a major step in the right direction.

Post by Luke Kenneth Casson Leighton
what would you suggest, here - leave the intermediary GND traces in
or take them out.

My suggestion here would be to remove the GND traces between differential pairs since we have established that we can't get 15mil clearance from the differential pair traces with the GND traces in place. We don't have enough room for that.

I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry. If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well. If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.

This is all based on the fact that we are using differential-mode transmission for the high-frequency HDMI signals.

Post by Luke Kenneth Casson Leighton
also, i think i "Get It" about the intermediary wiggles. when the
transmit end does automatic compensation that results in the signals
coming out in such a way that, really, the inter-pair length-matching
should be done from the *OPPOSITE* end i.e. from the CONNECTOR.

Maybe I misunderstood the standard because that wasn't my understanding. (All I know is second-hand because there are no freely available copies.) What I understood was:
1. The receiver has the capability to recover up to 5 bit times of inter-pair skew, resynchronizing the bit streams without any loss.
2. The standard takes this amount of time
max{T(recoverable inter-pair skew)} = 5 bit times = 0.5 * T(pixel)
for highest pixel clock supported under HDMI v1.4
max{f(pixel)} = 340MHz => T(pixel) = 2940ps
max{T(recoverable inter-pair skew)} = 1470ps
and allocates fractions of it to maximum inter-pair skew tolerances for the implementation of the HDMI transmitter (source of HDMI signal such as DVD player, video game console, or computer such as the EOMA68-A20), the HDMI cable, and the implementation of the HDMI receiver (sink of HDMI signal such as monitor, an HDMI-switching A/V receiver, an HDMI to VGA convertor).

Thus, in order to make an HDMI v1.4 standard-compliant transmitter (which is my understanding of what we are trying to do with the EOMA68-A20) we must emit from our HDMI connector an HDMI signal which exhibits
max{T(inter-pair skew)} <= 0.2 * T(pixel) = 588ps
This inter-pair skew can come from connector, the chip, and the PCB traces connecting them. It seems likely that the connector and the chip will likely be very minimal sources of inter-pair skew, and thus most, if not all, of the transmitter allocation falls to the PCB designer to use (or squander--depending on how you view it) in connecting the chip to the HDMI cable connector.

At the speed of propagation of signals in our microstrip differential pairs this amounts to
max{length(inter-pair skew)} = v(propagation) * max{T(inter-pair skew)}
= 150um/ps * 588ps = 88.2mm
Toradex suggests we limit the inter-pair skew in the traces to 1/4 of that value or 0.5 * T(bit) which corresponds to a length of 22mm.

From what I've seen, even without inter-pair skew compensation in the layout the inter-pair skew you observed was ~8mm < 22mm.

Post by Luke Kenneth Casson Leighton
because the automatic compensation will result in the signals coming
out with a small delay, which by the time they go round that big set
of bends they *WILL BE IN SYNC*.
ok they'll be in sync as long as all pairs are exactly the same
length from that point up until they meet the connector.
so the only bit that would be out-of-sync would be that huge set of
bends just after the transition from CPU-layer-1 onto layer 6, where
i've had to put in huge amounts of bend-compensation.
by adding in the down-stream inter-pair compensation just before the
rclamp0524p's) that *entire straight section* is out of sync... and
the set of bends is also out-of-sync so it's no improvement.

If this is indeed how it works then I'll need to rethink my recommendations. (I outlined my understanding above.)

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Are you talking about moving the differential pairs further
from the edge of the board?

yes. but from what you're saying it's not possible anyway.

How far are the differential traces from board edge at present?

[…]

Post by Luke Kenneth Casson Leighton
indeed. however i don't want to change the BOM, apart from anything
that's a TI part not a "Well Known Easily Sourceable Part In The Shenzhen
Huaqiang Road Eco-System".
dual rclamp0524's, one each side, it is.

I understand about part availability. For what it's worth, that document [SLLA324] concerns a TI part--TPD12S016 to be exact. It comes in both TSSOP and μQFN packages. The board layout we have been discussing in which they use the micro (type "D") connector they pair it with the μQFN package ESD part.
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[Luke Kenneth Casson Leighton]

On Thu, Aug 17, 2017 at 12:01 AM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
ahhhh ok. i'm glad you're paying attention :)

I'm trying ;>)

:)

Post by Richard Wilbur
[…]

Post by Luke Kenneth Casson Leighton
if i just take *out* the ground intermediary traces that would do the
trick of bringing the impedance back up, is that right?

Should be a major step in the right direction.

Post by Luke Kenneth Casson Leighton
what would you suggest, here - leave the intermediary GND traces in
or take them out.

My suggestion here would be to remove the GND traces between differential pairs since we have established that we can't get 15mil clearance from the differential pair traces with the GND traces in place. We don't have enough room for that.

ok.

Post by Richard Wilbur
I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry. If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well. If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.

flood-fill will just end up putting them back - i'd have to set a
copper-to-trace separation @ 15mil as well.

there's one place where the diffpairs go past the main power line
(IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd
be nervous about taking that out.

Post by Richard Wilbur
This is all based on the fact that we are using differential-mode transmission for the high-frequency HDMI signals.

Post by Luke Kenneth Casson Leighton
also, i think i "Get It" about the intermediary wiggles. when the
transmit end does automatic compensation that results in the signals
coming out in such a way that, really, the inter-pair length-matching
should be done from the *OPPOSITE* end i.e. from the CONNECTOR.

1. The receiver has the capability to recover up to 5 bit times of inter-pair skew,

o arse: *receiver* not transmitter.

Post by Richard Wilbur
Thus, in order to make an HDMI v1.4 standard-compliant transmitter (which is my understanding of what we are trying to do with the EOMA68-A20) we must emit from our HDMI connector an HDMI signal which exhibits
max{T(inter-pair skew)} <= 0.2 * T(pixel) = 588ps
This inter-pair skew can come from connector, the chip, and the PCB traces connecting them. It seems likely that the connector and the chip will likely be very minimal sources of inter-pair skew, and thus most, if not all, of the transmitter allocation falls to the PCB designer to use (or squander--depending on how you view it) in connecting the chip to the HDMI cable connector.
At the speed of propagation of signals in our microstrip differential pairs this amounts to
max{length(inter-pair skew)} = v(propagation) * max{T(inter-pair skew)}
= 150um/ps * 588ps = 88.2mm
Toradex suggests we limit the inter-pair skew in the traces to 1/4 of that value or 0.5 * T(bit) which corresponds to a length of 22mm.

22 mm... okaaay.

Post by Richard Wilbur
From what I've seen, even without inter-pair skew compensation in the layout the inter-pair skew you observed was ~8mm < 22mm.

9. or so. okaaay now i get it.

Post by Richard Wilbur
If this is indeed how it works then I'll need to rethink my recommendations. (I outlined my understanding above.)

nono, my mistake.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Are you talking about moving the differential pairs further
from the edge of the board?

yes. but from what you're saying it's not possible anyway.

How far are the differential traces from board edge at present?

0.9mm -> 35 mil.

to the nearest vias is 0.2mm -> 0.787mil

l.

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Post by Luke Kenneth Casson Leighton
On Thu, Aug 17, 2017 at 12:01 AM, Richard Wilbur

Post by Richard Wilbur
I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry. If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well. If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.

flood-fill will just end up putting them back - i'd have to set a

Isn't there a option to create barriers or free form where the
floodfill may not come, white spaces so to speak. Seems to me there
should be. You should be able to create "white" spots on the GND
planes for various reasons.

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[Luke Kenneth Casson Leighton]

Post by m***@gmail.com

Post by Luke Kenneth Casson Leighton
flood-fill will just end up putting them back - i'd have to set a

Isn't there a option to create barriers or free form where the
floodfill may not come, white spaces so to speak. Seems to me there
should be.

there is..... however that would mean having to maintain an exact
and specific mirror of the exact path of the traces, whereby any
changes *to* the exact and specific path of the traces would require a
corresponding, exact, specific and precisely and without fail 100%
matching change to that area.

total pain in the ass in other words.

... on the other hand simply changing *one parameter* in the design
rules achieves the exact same result... done dynamically and with no
fuss.

Post by m***@gmail.com
You should be able to create "white" spots on the GND
planes for various reasons.

indeed.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Thu, Aug 17, 2017 at 12:01 AM, Richard Wilbur

Post by Richard Wilbur
[…]
I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry. If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well. If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.

flood-fill will just end up putting them back - i'd have to set a

Sounds like just the ticket. So you have a flood-fill on the bottom layer? Is the flood-fill connected to GND? Can you set the 15mil copper-to-trace separation as a property of the differential traces?

The goal with this 15mil clearance is to space other copper in the same plane far enough away to have a negligible effect on the differential impedance of the differential pair and by the same token negligible high-frequency signal coupling. The microstrip differential pair geometry is based on having ground plane (may it extend forever ;>) underneath the traces separated by a dielectric of thickness t. (We took that into account in the impedance calculations. Actually power and ground are identical from the perspective of high-frequency signals so we could have built our microstrip differential pair over a power plane--or even moved from one reference plane to another. If we change reference planes, then we need to provide a low-impedance at high frequency path for any return current. Since we used two different ground planes, plated through-hole vias work well. If we had used planes at different potentials we would couple through capacitors.)

Post by Luke Kenneth Casson Leighton
there's one place where the diffpairs go past the main power line
(IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd
be nervous about taking that out.

I wouldn't worry because that 5mil copper GND has 5mil spacing on each side, thus ensuring 15mil between the closest differential trace and power. That should be sufficient.

On the other hand, if I remember correctly the proximity to IPSOUT happened because we decided to do significant inter-pair skew compensation close to the power circuit. If we remove that inter-pair compensation, we may have enough space to keep that ground trace around IPSOUT and still make our 15mil clearance around the differential pairs.

The other thing that we can do if we have a little extra space after taking out the intermediary GND shield traces and inter-pair skew compensation wiggles is distribute the intra-pair skew compensation closer to the sources of intra-pair skew--corners. Right now you've done a great job of compensating for intra-pair skew in the first segment: from CPU lands to first via. Then there are some very significant wiggles when we first get to the bottom layer and I don't see any other intra-pair skew compensation all the way out to the connector.

If we can do it, the most effective place for intra-pair skew compensation is within 15mil of the skew source--right before or after a bend. If skew originates in a bend and is resolved by a complementary bend within 15mils, then we don't need to add anything specific.

If we distribute the intra-pair skew compensation as outlined above we will likely be able to accomplish it with some pretty small wiggles which may fit more easily into the available space.

[…]

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
1. The receiver has the capability to recover up to 5 bit times of inter-pair skew,

o arse: *receiver* not transmitter.

No problem then. But it sure highlights the importance of having the correct perspective when thinking about the problem.:) (I have trouble with it too, at times. The right perspective often makes the problem much more tractable.)

[…]

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Toradex suggests we limit the inter-pair skew in the traces to 1/4 of that value or 0.5 * T(bit) which corresponds to a length of 22mm.

22 mm... okaaay.

Post by Richard Wilbur
From what I've seen, even without inter-pair skew compensation in the layout the inter-pair skew you observed was ~8mm < 22mm.

9. or so. okaaay now i get it.

You can see how I came to the conclusion that we will likely be fine without any inter-pair skew compensation--with even a pretty generous engineering margin.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Are you talking about moving the differential pairs further
from the edge of the board?

yes. but from what you're saying it's not possible anyway.

How far are the differential traces from board edge at present?

0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil

How far is the board-edge ground shield trace from the edge of the board? From the closest differential pair trace? How wide is the board-edge ground shield trace?

I'm guessing you meant the closest vias to the differential pair traces are 0.2mm = 7.87mil? Are these the ground-to-ground vias for low-impedance connection of reference planes? (Low-impedance return path close to signal vias?)
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[Luke Kenneth Casson Leighton]

On Thu, Aug 17, 2017 at 5:20 PM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
flood-fill will just end up putting them back - i'd have to set a

Sounds like just the ticket. So you have a flood-fill on the bottom layer?

all layers.

Post by Richard Wilbur
Is the flood-fill connected to GND?

only when it's properly arranged to be so... i.e. when you don't you
get a warning... short answer: yes.

Post by Richard Wilbur
Can you set the 15mil copper-to-trace separation as a property of the differential traces?

yyup. i really like PADS for this reason

Post by Richard Wilbur
The goal with this 15mil clearance is to space other copper
in the same plane far enough away to have a negligible effect
on the differential impedance of the differential pair and by the
same token negligible high-frequency signal coupling.

okaaay. i get it.

Post by Richard Wilbur
The microstrip differential pair geometry is based on having ground
plane (may it extend forever ;>)

:)

Post by Richard Wilbur
underneath the traces separated by a dielectric of thickness t.
(We took that into account in the impedance calculations.

yehyeh.

Post by Richard Wilbur
Actually power and ground are identical from the perspective of
high-frequency signals so we could have built our microstrip
differential pair over a power plane--or even moved from one
reference plane to another.

ohhh that explains why DDR3 has a big power-plane @ the 1/2 way
"reference" voltage. nice.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
there's one place where the diffpairs go past the main power line
(IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd
be nervous about taking that out.

I wouldn't worry because that 5mil copper GND has
5mil spacing on each side, thus ensuring 15mil between the closest
differential trace and power. That should be sufficient.

... need to check it.

Post by Richard Wilbur
On the other hand, if I remember correctly the proximity to IPSOUT
happened because we decided to do significant inter-pair skew
compensation close to the power circuit.

ah no: it's always been very close: in this revision i particularly
wanted the vias left of the rclamp0524p to be reasonably symmetrical
and clean, with a straight (diff-paired) path to the rclamp0524p
instead of taking a turn to get to it (as in previous revisions).

that required a little bit more space, which meant moving IPSOUT's
vias a little bit further over. i could _probably_ move them over a
bit further...

Post by Richard Wilbur
The other thing that we can do if we have a little extra space
after taking out the intermediary GND shield traces and inter-pair
skew compensation wiggles is distribute the intra-pair skew
compensation closer to the sources of intra-pair skew--corners.

aw poop - changing those is quite a task. there's some bugs due to a
combination of grid snap and push-and-shove in PADS where removing the
long straights means i can't add them back in again. and i need to
remove them because otherwise i don't know how long the traces are
from the vias. what i do is:

* remove the long sections
* re-add a *short* diffpair section of only about 1mm
* those end up being equal length
* then because the traces aren't complete PADS will tell you exactly
how long they are
* therefore i can now measure them both and...
* therefore i know exactly how much manual "wiggle" to put in the shorter one.

once the wiggles are done i can re-add the long sections, confident
that the signals will be matched.

but it's a pain to do! :)

Post by Richard Wilbur
Right now you've done a great job of compensating for intra-pair
skew in the first segment: from CPU lands to first via.

yehyeh. they're near-identical.

Post by Richard Wilbur
Then there are some very significant wiggles when we first get
to the bottom layer

yes. intra-pair correction due to wanting to have the 1st layer
traces all the same length. it's nearly... 1.5mm to correct, due to
not just the offset of the vias but also the turn. if i tried to
stagger those first vias the other way (which i tried once) then
there's not enough room to have those 1st trace segments be equal
length...

Post by Richard Wilbur
and I don't see any other intra-pair skew
compensation all the way out to the connector.

that's because they're all fine... ok i read somewhere that it's ok
to have some intra-pair skew on short lengths between turns. sooOo...
i'm assuming that the critical part is the long straight. sooOOo i
arranged for the wiggles to make perfect length-matching just as each
pair hits the beginning of each long straight.

now (and i've removed the inter-pair skew in the current revision)
what i *haven't* done is add in any inter-skew correction at the
points marked in green (attached). i'm assuming that those diagonal
cross-paths (between each green ring) are... within acceptable
tolerance for intra-skew.

Post by Richard Wilbur
If we can do it, the most effective place for intra-pair skew compensation
is within 15mil of the skew source--right before or after a bend.
If skew originates in a bend and is resolved by a complementary bend within 15mils,
then we don't need to add anything specific.

mmmm *grumble, grumble*.... i think there might be space to add them,
around where the green rings are, by moving the diagonal pieces to the
right a bit.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
How far are the differential traces from board edge at present?

0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil

How far is the board-edge ground shield trace
from the edge of the board?

to the edge of the GND shield trace: 0.46mm -> 18 mil

Post by Richard Wilbur
From the closest differential pair trace?

to the edge of the CK diffpair, 0.93mm -> 36.6 mil

Post by Richard Wilbur
How wide is the board-edge ground shield trace?

pffh :) peanuts. very tight. 13 mil (that's to the vias as well,
which i realise is slightly dodgy).

Post by Richard Wilbur
I'm guessing you meant the closest vias to the differential pair
traces are 0.2mm = 7.87mil?

yyep.

Post by Richard Wilbur
Are these the ground-to-ground vias for low-impedance connection
of reference planes? (Low-impedance return path close to signal vias?)

honestly i haven't been thinking in terms so specific: i just add
them arbitrarily because i heard it was the right thing to do!
learning fast...

l.

[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Thu, Aug 17, 2017 at 5:20 PM, Richard Wilbur

[…]

Post by Luke Kenneth Casson Leighton
So you have a flood-fill on the bottom layer?
all layers.

Post by Richard Wilbur
Is the flood-fill connected to GND?

only when it's properly arranged to be so... i.e. when you don't you
get a warning... short answer: yes.

Post by Richard Wilbur
Can you set the 15mil copper-to-trace separation as a property of the differential traces?

yyup. i really like PADS for this reason

Post by Richard Wilbur
The goal with this 15mil clearance is to space other copper
in the same plane far enough away to have a negligible effect
on the differential impedance of the differential pair and by the
same token negligible high-frequency signal coupling.

okaaay. i get it.

Post by Richard Wilbur
The microstrip differential pair geometry is based on having ground
plane (may it extend forever ;>)

:)

Post by Richard Wilbur
underneath the traces separated by a dielectric of thickness t.
(We took that into account in the impedance calculations.

yehyeh.

Post by Richard Wilbur
Actually power and ground are identical from the perspective of
high-frequency signals so we could have built our microstrip
differential pair over a power plane--or even moved from one
reference plane to another.

"reference" voltage. nice.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
there's one place where the diffpairs go past the main power line
(IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd
be nervous about taking that out.

I wouldn't worry because that 5mil copper GND has
5mil spacing on each side, thus ensuring 15mil between the closest
differential trace and power. That should be sufficient.

... need to check it.

Post by Richard Wilbur
On the other hand, if I remember correctly the proximity to IPSOUT
happened because we decided to do significant inter-pair skew
compensation close to the power circuit.

ah no: it's always been very close: in this revision i particularly
wanted the vias left of the rclamp0524p to be reasonably symmetrical
and clean, with a straight (diff-paired) path to the rclamp0524p
instead of taking a turn to get to it (as in previous revisions).
that required a little bit more space, which meant moving IPSOUT's
vias a little bit further over. i could _probably_ move them over a
bit further...

Post by Richard Wilbur
The other thing that we can do if we have a little extra space
after taking out the intermediary GND shield traces and inter-pair
skew compensation wiggles is distribute the intra-pair skew
compensation closer to the sources of intra-pair skew--corners.

aw poop - changing those is quite a task. there's some bugs due to a
combination of grid snap and push-and-shove in PADS where removing the
long straights means i can't add them back in again. and i need to
remove them because otherwise i don't know how long the traces are
* remove the long sections
* re-add a *short* diffpair section of only about 1mm
* those end up being equal length
* then because the traces aren't complete PADS will tell you exactly
how long they are
* therefore i can now measure them both and...
* therefore i know exactly how much manual "wiggle" to put in the shorter one.
once the wiggles are done i can re-add the long sections, confident
that the signals will be matched.
but it's a pain to do! :)

Post by Richard Wilbur
Right now you've done a great job of compensating for intra-pair
skew in the first segment: from CPU lands to first via.

yehyeh. they're near-identical.

Post by Richard Wilbur
Then there are some very significant wiggles when we first get
to the bottom layer

yes. intra-pair correction due to wanting to have the 1st layer
traces all the same length. it's nearly... 1.5mm to correct, due to
not just the offset of the vias but also the turn. if i tried to
stagger those first vias the other way (which i tried once) then
there's not enough room to have those 1st trace segments be equal
length...

Post by Richard Wilbur
and I don't see any other intra-pair skew
compensation all the way out to the connector.

that's because they're all fine... ok i read somewhere that it's ok
to have some intra-pair skew on short lengths between turns. sooOo...
i'm assuming that the critical part is the long straight. sooOOo i
arranged for the wiggles to make perfect length-matching just as each
pair hits the beginning of each long straight.
now (and i've removed the inter-pair skew in the current revision)
what i *haven't* done is add in any inter-skew correction at the
points marked in green (attached). i'm assuming that those diagonal
cross-paths (between each green ring) are... within acceptable
tolerance for intra-skew.

Post by Richard Wilbur
If we can do it, the most effective place for intra-pair skew compensation
is within 15mil of the skew source--right before or after a bend.
If skew originates in a bend and is resolved by a complementary bend within 15mils,
then we don't need to add anything specific.

mmmm *grumble, grumble*.... i think there might be space to add them,
around where the green rings are, by moving the diagonal pieces to the
right a bit.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
How far are the differential traces from board edge at present?

0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil

How far is the board-edge ground shield trace
from the edge of the board?

to the edge of the GND shield trace: 0.46mm -> 18 mil

Post by Richard Wilbur
From the closest differential pair trace?

to the edge of the CK diffpair, 0.93mm -> 36.6 mil

Post by Richard Wilbur
How wide is the board-edge ground shield trace?

pffh :) peanuts. very tight. 13 mil (that's to the vias as well,
which i realise is slightly dodgy).

Post by Richard Wilbur
I'm guessing you meant the closest vias to the differential pair
traces are 0.2mm = 7.87mil?

yyep.

Post by Richard Wilbur
Are these the ground-to-ground vias for low-impedance connection
of reference planes? (Low-impedance return path close to signal vias?)

honestly i haven't been thinking in terms so specific: i just add
them arbitrarily because i heard it was the right thing to do!
learning fast...
l.
<Untitled.jpg>
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whoops looks like you hit reply early, richard! :)

On Sat, Aug 19, 2017 at 3:07 PM, Richard Wilbur

Post by Luke Kenneth Casson Leighton
<Untitled.jpg>

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Post by Luke Kenneth Casson Leighton
whoops looks like you hit reply early, richard! :)

Yes! My apologies to everyone on the list. I am working on a more substantive reply but didn't get it finished or sent yesterday before I did several hours of driving (southeast from Seattle, Washington into northern Oregon). Today several more hours of driving to reach an area where we can observe the total solar eclipse tomorrow morning. (I'm on vacation with my family.)
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On Sun, Aug 20, 2017 at 2:58 PM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
whoops looks like you hit reply early, richard! :)

Today several more hours of driving to reach an area where we can
observe the total solar eclipse tomorrow morning.
(I'm on vacation with my family.)

nice! yeh the lunar eclipse was... eclipsed by clouds here in taipei.

l.

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Post by Luke Kenneth Casson Leighton
nice! yeh the lunar eclipse was... eclipsed by clouds here in taipei.

Sorry to hear that. My family saw a lunar eclipse several years ago and it was quiet and beautiful. It happened in the wee hours of the morning so my wife and I got the kids up, bundled them into the car and drove half a mile to a field where we had a great view. So I recommend it--if you can get the weather to cooperate! ;>)
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Post by Luke Kenneth Casson Leighton
On Thu, Aug 17, 2017 at 5:20 PM, Richard Wilbur

Post by Richard Wilbur
So you have a flood-fill on the bottom layer?

all layers.

Post by Richard Wilbur
Is the flood-fill connected to GND?

only when it's properly arranged to be so... i.e. when you don't you
get a warning... short answer: yes.

So it sounds to me like some of the ground vias can connect more than just layers 2 and 5 if they happen to coincide with ground flood-fill on one or more other layers?

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Can you set the 15mil copper-to-trace separation as a property of the differential traces?

yyup. i really like PADS for this reason

Nice.

[…]

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
there's one place where the diffpairs go past the main power line
(IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd
be nervous about taking that out.

I wouldn't worry because that 5mil copper GND has
5mil spacing on each side, thus ensuring 15mil between the closest
differential trace and power. That should be sufficient.

... need to check it.

Those were my understanding of the limits of your board fabricator:
min{spacing} = 5mil
min{trace width} = 5mil

Post by Luke Kenneth Casson Leighton
it's always been very close: in this revision i particularly
wanted the vias left of the rclamp0524p to be reasonably symmetrical
and clean, with a straight (diff-paired) path to the rclamp0524p
instead of taking a turn to get to it (as in previous revisions).
that required a little bit more space, which meant moving IPSOUT's
vias a little bit further over. i could _probably_ move them over a
bit further...

Sounds fine.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
The other thing that we can do if we have a little extra space
after taking out the intermediary GND shield traces and inter-pair
skew compensation wiggles is distribute the intra-pair skew
compensation closer to the sources of intra-pair skew--corners.

aw poop - changing those is quite a task. there's some bugs due to a
combination of grid snap and push-and-shove in PADS where removing the
long straights means i can't add them back in again. and i need to
remove them because otherwise i don't know how long the traces are
* remove the long sections
* re-add a *short* diffpair section of only about 1mm
* those end up being equal length
* then because the traces aren't complete PADS will tell you exactly
how long they are
* therefore i can now measure them both and...
* therefore i know exactly how much manual "wiggle" to put in the shorter one.
once the wiggles are done i can re-add the long sections, confident
that the signals will be matched.
but it's a pain to do! :)

I'm glad you have a method that works. I'm sorry it is such a pain. Too bad it isn't more straightforward. Is PADS libre software? I ask because here's an itch.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Right now you've done a great job of compensating for intra-pair
skew in the first segment: from CPU lands to first via.

yehyeh. they're near-identical.

Post by Richard Wilbur
Then there are some very significant wiggles when we first get
to the bottom layer

yes. intra-pair correction due to wanting to have the 1st layer
traces all the same length. it's nearly... 1.5mm to correct, due to
not just the offset of the vias but also the turn. if i tried to
stagger those first vias the other way (which i tried once) then
there's not enough room to have those 1st trace segments be equal
length...

Post by Richard Wilbur
and I don't see any other intra-pair skew
compensation all the way out to the connector.

that's because they're all fine... ok i read somewhere that it's ok
to have some intra-pair skew on short lengths between turns. sooOo...
i'm assuming that the critical part is the long straight. sooOOo i
arranged for the wiggles to make perfect length-matching just as each
pair hits the beginning of each long straight.
now (and i've removed the inter-pair skew in the current revision)
what i *haven't* done is add in any inter-skew correction at the
points marked in green (attached). i'm assuming that those diagonal
cross-paths (between each green ring) are... within acceptable
tolerance for intra-skew.

Post by Richard Wilbur
If we can do it, the most effective place for intra-pair skew compensation
is within 15mil of the skew source--right before or after a bend.
If skew originates in a bend and is resolved by a complementary bend within 15mils,
then we don't need to add anything specific.

mmmm *grumble, grumble*.... i think there might be space to add them,
around where the green rings are, by moving the diagonal pieces to the
right a bit.

Sounds like a good plan. How much intra-pair skew do we incur at each of those bends?

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
How far are the differential traces from board edge at present?

0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil

How far is the board-edge ground shield trace
from the edge of the board?

to the edge of the GND shield trace: 0.46mm -> 18 mil

Post by Richard Wilbur
From the closest differential pair trace?

to the edge of the CK diffpair, 0.93mm -> 36.6 mil

Post by Richard Wilbur
How wide is the board-edge ground shield trace?

pffh :) peanuts. very tight. 13 mil (that's to the vias as well,
which i realise is slightly dodgy).

We'll take what we can fit.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
I'm guessing you meant the closest vias to the differential pair
traces are 0.2mm = 7.87mil?

yyep.

In order for me to understand better the dimensions you're quoting allow me to resort to a diagram.

edge of the world/board
|<- spacing to first Cu ->|
v |<-width of ground shield trace ->|<-spacing to diff. pair->|CLK-
FR-4 substrateFR-4 substrateFR-4 substrateFR-4 substrateFR-4 substrate

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Are these the ground-to-ground vias for low-impedance connection
of reference planes? (Low-impedance return path close to signal vias?)

honestly i haven't been thinking in terms so specific: i just add
them arbitrarily because i heard it was the right thing to do!
learning fast...

It is good to have a scattering of vias connecting related planes (in this case ground). With limited space it becomes more important to use what heuristic we can muster to place them strategically.

(Writing from our tent here in John Day, Oregon. The total solar eclipse yesterday morning was spectacular. I'm glad we travelled to be in the path of totality. I've seen partial solar eclipses before but this was well worth the trip. We're going to visit the John Day Fossil Beds today before we head home tomorrow.)
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On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
On Thu, Aug 17, 2017 at 5:20 PM, Richard Wilbur

Post by Richard Wilbur
So you have a flood-fill on the bottom layer?

all layers.

Post by Richard Wilbur
Is the flood-fill connected to GND?

only when it's properly arranged to be so... i.e. when you don't you
get a warning... short answer: yes.

So it sounds to me like some of the ground vias can connect more than just layers 2 and 5 if they happen to coincide with ground flood-fill on one or more other layers?

yehyeh, they go all the way through and connect to all layers 1
through 6 if there's flood-fill or a GND trace on any of them.

Post by Richard Wilbur
min{spacing} = 5mil
min{trace width} = 5mil

yeah it's more what i set so things don't get ridiculously
expensive... but yes.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
it's always been very close: in this revision i particularly
wanted the vias left of the rclamp0524p to be reasonably symmetrical
and clean, with a straight (diff-paired) path to the rclamp0524p
instead of taking a turn to get to it (as in previous revisions).
that required a little bit more space, which meant moving IPSOUT's
vias a little bit further over. i could _probably_ move them over a
bit further...

Sounds fine.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
The other thing that we can do if we have a little extra space
after taking out the intermediary GND shield traces and inter-pair
skew compensation wiggles is distribute the intra-pair skew
compensation closer to the sources of intra-pair skew--corners.

aw poop - changing those is quite a task. there's some bugs due to a
combination of grid snap and push-and-shove in PADS where removing the
long straights means i can't add them back in again. and i need to
remove them because otherwise i don't know how long the traces are
* remove the long sections
* re-add a *short* diffpair section of only about 1mm
* those end up being equal length
* then because the traces aren't complete PADS will tell you exactly
how long they are
* therefore i can now measure them both and...
* therefore i know exactly how much manual "wiggle" to put in the shorter one.
once the wiggles are done i can re-add the long sections, confident
that the signals will be matched.
but it's a pain to do! :)

I'm glad you have a method that works. I'm sorry it is such a pain. Too bad it isn't more straightforward. Is PADS libre software? I ask because here's an itch.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Right now you've done a great job of compensating for intra-pair
skew in the first segment: from CPU lands to first via.

yehyeh. they're near-identical.

Post by Richard Wilbur
Then there are some very significant wiggles when we first get
to the bottom layer

yes. intra-pair correction due to wanting to have the 1st layer
traces all the same length. it's nearly... 1.5mm to correct, due to
not just the offset of the vias but also the turn. if i tried to
stagger those first vias the other way (which i tried once) then
there's not enough room to have those 1st trace segments be equal
length...

Post by Richard Wilbur
and I don't see any other intra-pair skew
compensation all the way out to the connector.

that's because they're all fine... ok i read somewhere that it's ok
to have some intra-pair skew on short lengths between turns. sooOo...
i'm assuming that the critical part is the long straight. sooOOo i
arranged for the wiggles to make perfect length-matching just as each
pair hits the beginning of each long straight.
now (and i've removed the inter-pair skew in the current revision)
what i *haven't* done is add in any inter-skew correction at the
points marked in green (attached). i'm assuming that those diagonal
cross-paths (between each green ring) are... within acceptable
tolerance for intra-skew.

Post by Richard Wilbur
If we can do it, the most effective place for intra-pair skew compensation
is within 15mil of the skew source--right before or after a bend.
If skew originates in a bend and is resolved by a complementary bend within 15mils,
then we don't need to add anything specific.

mmmm *grumble, grumble*.... i think there might be space to add them,
around where the green rings are, by moving the diagonal pieces to the
right a bit.

Sounds like a good plan. How much intra-pair skew do we incur at each of those bends?

very little. it's a 45 degree bend in each case so.... can probably
work out the maths... 15mil separation...

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
How far are the differential traces from board edge at present?

0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil

How far is the board-edge ground shield trace
from the edge of the board?

to the edge of the GND shield trace: 0.46mm -> 18 mil

Post by Richard Wilbur
From the closest differential pair trace?

to the edge of the CK diffpair, 0.93mm -> 36.6 mil

Post by Richard Wilbur
How wide is the board-edge ground shield trace?

pffh :) peanuts. very tight. 13 mil (that's to the vias as well,
which i realise is slightly dodgy).

We'll take what we can fit.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
I'm guessing you meant the closest vias to the differential pair
traces are 0.2mm = 7.87mil?

yyep.

In order for me to understand better the dimensions you're quoting allow me to resort to a diagram.
edge of the world/board
|<- spacing to first Cu ->|
v |<-width of ground shield trace ->|<-spacing to diff. pair->|CLK-
FR-4 substrateFR-4 substrateFR-4 substrateFR-4 substrateFR-4 substrate

urk. attached diagram is probably a lot easier. i also checked the
Design Rules: board-to-everything-and-anything is set to 11.84 mil,
everything-else-to-anything-else is set to 5mil.

so in the attached diagram those traces i put right at the bottom
will be overwritten by about... 1.2 mil to make up to the 11.84
board-to-copper clearance.

so, actually very simple. everything-to-everything-but-board: 5mil.
board-to-everything: 11.84mil.

Post by Richard Wilbur
(Writing from our tent here in John Day, Oregon. The total solar eclipse yesterday morning was spectacular. I'm glad we travelled to be in the path of totality. I've seen partial solar eclipses before but this was well worth the trip. We're going to visit the John Day Fossil Beds today before we head home tomorrow.)

niice :)

[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur

Post by Richard Wilbur
Is PADS libre software? I ask because here's an itch.

I looked for myself and found PADS[*] is a product of Mentor Graphics. Looks like a nice tool, but I guess I don't have to worry about submitting a patch. ;>)

Reference:
[*] https://www.pads.com/
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On Sun, Aug 27, 2017 at 7:36 PM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur

Post by Richard Wilbur
Is PADS libre software? I ask because here's an itch.

I looked for myself and found PADS[*] is a product of Mentor Graphics.

yyep. absolutely awesome one, too. i'm recommending it constantly
to people, not just in the libre world but also those who use
proprietary tools as well. the learning curve is nowhere near as
steep as with other proprietary tools. ORCAD is completely insane: 20
menus with over 30 options on each. totally user-hostile.

PADS: everything is context-sensitive, and the menu options show you a
graphical representation (2D cutaway or overhead view) of what you
just selected. absolutely superb.

Post by Richard Wilbur
Looks like a nice tool, but I guess I don't have to worry about submitting a patch. ;>)

love to... but ehhmmm.. no :)

l.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur

Post by Richard Wilbur
How much intra-pair skew do we incur at each of those bends?

very little. it's a 45 degree bend in each case so.... can probably
work out the maths... 15mil separation...

Between traces of the same differential pair (intra-pair) I would have expected 5mil separation.

I'm not entirely sure how PADS does the trace length calculation:
1. Is it measuring the inside edges of the differential pair traces? Then the intra-pair skew from one 45° corner would be 5mil.
2. Is it measuring the centers of the 5mil wide traces? If so I'd expect the intra-pair skew to be 10mil.
3. It may be measuring in a different way of which I'm not thinking.

Post by Luke Kenneth Casson Leighton
attached diagram is probably a lot easier. i also checked the
Design Rules: board-to-everything-and-anything is set to 11.84 mil,
everything-else-to-anything-else is set to 5mil.
so in the attached diagram those traces i put right at the bottom
will be overwritten by about... 1.2 mil to make up to the 11.84
board-to-copper clearance.

Does that mean that flood fill will cover out from 13mil off the board edge (as noted in the diagram) up to the 11.84mil board-to-copper clearance?

Post by Luke Kenneth Casson Leighton
so, actually very simple. everything-to-everything-but-board: 5mil.
board-to-everything: 11.84mil.

Simple is good--only as complicated as it needs to be.
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On Mon, Aug 28, 2017 at 10:13 PM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur

Post by Richard Wilbur
How much intra-pair skew do we incur at each of those bends?

very little. it's a 45 degree bend in each case so.... can probably
work out the maths... 15mil separation...

Between traces of the same differential pair (intra-pair) I would have expected 5mil separation.

sorry i was referring to outer-edge to outer-edge so 5 trace + 5 gap + 5 tracee
no idea. it's most likely to be down the middle.

Post by Richard Wilbur
2. Is it measuring the centers of the 5mil wide traces? If so I'd expect the intra-pair skew to be 10mil.

true! this i would expect.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
so in the attached diagram those traces i put right at the bottom
will be overwritten by about... 1.2 mil to make up to the 11.84
board-to-copper clearance.

Does that mean that flood fill will cover out from 13mil
off the board edge (as noted in the diagram) up to the
11.84mil board-to-copper clearance?

remember i mentioned that the flood-fill has some "curvature" rules
on it: if the radius (a parameter somewhere) is too small the
flood-fill won't go in there.

example attached: see green arrow, the track "jigs" in just at that
point. grey is the flood outline btw. at that point the radius of
the grey flood-fill just below the green arrow is too small, so the
flood-fill refuses to go into the gap between the board edge and the
track with the "jig" in it.

so instead what i have to do here is to make that "manual" GND track
11 or so mil wide, and that does the trick.

anyway *apart* from those special circumstances, what will happen in
the case you refer to is that PADS will create a tiny bit of GND
copper (13-11.84 = 1.16mm) wide just *below* that VIA's outer edge,
including covering the via itself.

so.. yes! that's actually shown in the 2nd picture. i selected
(highlighted) the VIA, and you can see how the flood-fill outline
(grey) overlaps the entire VIA (outer extent of which is 13mm from the
board edge) but the flood comes *no closer* than it is told to, which
is 11.84mm.

basically the VIA - which is a GND via - is totally irrelevant to the
distance / extent that the flood fill goes to the board edge. now if
that VIA was NOT a part of the GND net *THEN* the flood fill would
avoid THAT via (by the amount set in the Design Rules). but if it's
the same net, flood fill "ignores" it in effect (and just floods over
it as if it wasn't there).

l.

[Richard Wilbur]

On Aug 22, 2017, at 08:13, Luke Kenneth Casson Leighton <***@lkcl.net> wrote:

Looking at your cool diagram from 22 Aug, the ground trace at the bottom of the board looks like it is 5mil wide as it appears the same width as HTXCN et al. That assumption together with the dimensions you provide leads me to believe that we can nearly have our cake and eat too!
distance from ground trace to closest differential trace = 37mil from board edge to closest differential trace - 18mil from board edge to ground trace - 5mil ground trace width = 14mil

I notice that the via copper extends to 13mil from board edge. Thus, if we were to move the ground trace down 1mil, we would have 15mil spacing to the closest differential trace without breaking the 11.84mil board edge clearance. (Vias would extend to 12mil from board edge.)

This is good for impedance on the differential pair next to the board edge, HTXC = HDMI transmit clock. The vias will encroach closer. Can we trim the pad on the side towards the differential trace to reduce the encroachment?


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Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
if i just take *out* the ground intermediary traces that would do the
trick of bringing the impedance back up, is that right?

Should be a major step in the right direction.

How about the ground plane below the traces... That's a major stray
capacitance and closer than the "narrow" surrounding GND traces?

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Post by m***@gmail.com
How about the ground plane below the traces... That's a major stray
capacitance and closer than the "narrow" surrounding GND traces?

good question!

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[Richard Wilbur]

Post by m***@gmail.com

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
if i just take *out* the ground intermediary traces that would do the
trick of bringing the impedance back up, is that right?

Should be a major step in the right direction.

How about the ground plane below the traces... That's a major stray
capacitance and closer than the "narrow" surrounding GND traces?

The ground plane would be stray except we designed it into the single-ended and differential impedance. At this point it is integral to our differential microstrip geometry. (See my original post in the thread "HDMI High-Frequency Layout: Impedance".)
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Post by Richard Wilbur

Post by m***@gmail.com

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
if i just take *out* the ground intermediary traces that would do the
trick of bringing the impedance back up, is that right?

Should be a major step in the right direction.

After thinking it through I have to agree. Each GND trace would become
coupled with the diff pairs. Effectively creating a link between two
pairs. Which we do not want.

Post by Richard Wilbur

Post by m***@gmail.com
How about the ground plane below the traces... That's a major stray
capacitance and closer than the "narrow" surrounding GND traces?

The ground plane would be stray except we designed it into the single-ended and differential impedance. At this point it is integral to our differential microstrip geometry. (See my original post in the thread "HDMI High-Frequency Layout: Impedance".)

I'll read that again.

I guess we just need to make sure that no other GND loop crosses the
HDMI plane. Perhaps create a barrier on the GND that follows the outer
HDMI traces. To prevent unwanted GND loops

http://www.ti.com/lit/ml/slyp173/slyp173.pdf

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Post by m***@gmail.com
I guess we just need to make sure that no other GND loop crosses the
HDMI plane. Perhaps create a barrier on the GND that follows the outer
HDMI traces. To prevent unwanted GND loops
http://www.ti.com/lit/ml/slyp173/slyp173.pdf

(Thank you for the link to another interesting high-frequency circuit and PCB layout reference. It concentrates on analog circuits but still has good wisdom and recommendations.)

Since we are routing the highest speed signals as a differential pair, and to the extent that we are able to create a differential microstrip transmission line, our biggest return current will be through the neighboring trace of the differential pair.

Since our differential microstrip transmission line will not be perfect, we are using ground vias to provide a low-impedance path for return currents across changes in the associated ground plane.

You bring up an interesting point: what other current return paths are in the same vicinity? I have not analyzed that in any detail. At least there are no other lines from signal source to signal sink that I know of that cross the region of the board where the high-frequency HDMI signals are routed. Also, to my knowledge we don't have segmented or restricted ground planes that would isolate regions with a higher-impedance reference.
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[Luke Kenneth Casson Leighton]

On Fri, Aug 18, 2017 at 5:51 PM, Richard Wilbur

Post by Richard Wilbur
You bring up an interesting point: what other current return paths are in the same vicinity? I have not analyzed that in any detail. At least there are no other lines from signal source to signal sink that I know of that cross the region of the board where the high-frequency HDMI signals are routed. Also, to my knowledge we don't have segmented or restricted ground planes that would isolate regions with a higher-impedance reference.

CEC etc. all follow roughly the same path, on layer 3 (separated by GND).

i just noticed that SD0 runs round the back of the HDMI 1st set of
VIAS (with no GND separation) on layer 3 - i've removed the SATA power
(not being used) so i can shift them up a bit

some GPIOs cross on layer 3 as well, just near the GND shielding near
those first vias...

not much.

l.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Fri, Aug 18, 2017 at 5:51 PM, Richard Wilbur

Post by Richard Wilbur
You bring up an interesting point: what other current return paths are in the same vicinity? I have not analyzed that in any detail. At least there are no other lines from signal source to signal sink that I know of that cross the region of the board where the high-frequency HDMI signals are routed. Also, to my knowledge we don't have segmented or restricted ground planes that would isolate regions with a higher-impedance reference.

CEC etc. all follow roughly the same path, on layer 3 (separated by GND).
i just noticed that SD0 runs round the back of the HDMI 1st set of
VIAS (with no GND separation) on layer 3 - i've removed the SATA power
(not being used) so i can shift them up a bit
some GPIOs cross on layer 3 as well, just near the GND shielding near
those first vias...
not much.

Layer 3 always has ground separation from layer 1 in the intervening ground plane on layer 2 and likewise from layer 6 by layers 4 and 5. So I'm not worried about those signals.

Regarding the SATA power: Is it an important part of providing a SATA interface? If so, I would suggest not limiting our options on this card. My understanding is that SATA is significantly more efficient for harddisk data interface than USB.

Regarding SD0: To what interface does it belong? What is the maximum data rate on this line?
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[Luke Kenneth Casson Leighton]

On Tue, Aug 22, 2017 at 4:30 PM, Richard Wilbur

Post by Richard Wilbur
Layer 3 always has ground separation from layer 1 in the intervening ground plane on layer 2 and likewise from layer 6 by layers 4 and 5. So I'm not worried about those signals.

ok great.

Post by Richard Wilbur
Regarding the SATA power: Is it an important part of providing a SATA interface? If so, I would suggest not limiting our options on this card. My understanding is that SATA is significantly more efficient for harddisk data interface than USB.

SATA was on a very preliminary version of EOMA68. it was cut a long time ago.

Post by Richard Wilbur
Regarding SD0: To what interface does it belong? What is the maximum data rate on this line?

MicroSD card reading (and other SD/MMC / SDIO compatible interfaces).
i *think* it's a max datarate of 50mhz....

l.

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[Luke Kenneth Casson Leighton]

okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i
can shorten even more, there's definitely plenty of space there, big
gap.

2nd image, right end, this is where i've added intra-pair wiggles at
the 45 degree bends. i can't get away with a proper 4-turn using 45
degrees, PADS goes "nope that's too short a trace, i'm gonna assume
you want a straight line instead" - there's probably an option
somewhere for that but i've not found it. alternatively i can add in
a (curvy) accordion....

anyway those wiggles are done by hand, some of them aren't pretty but
in mil those traces are now nearly all to within 0.01 mil. i cheat a
little and have made some of the corners in places a very very tiny
arc, where you get better fine-grain control over the amount it takes
off.

HTXCN just before the diff-pair vias at the end i'm a little concerned
about, it looks a bit too... sharp-angled to make me feel totally
comfortable... not a lot of space... i tried a single wiggle and it
went too far away from HTXCP for me to feel happy about it.... put in
two much smaller wiggles instead...

GND i'll remove as the absolute last thing.

l.

[Luke Kenneth Casson Leighton]

damn. i just noticed: the via transition here is at 90 degrees.
i've been switching off except 1 layer at a time so didn't notice.
arse.

i'll need to shift all but the TX2 via set down a fixed amount so i
can get a second wiggle in the right-hand one one layer 1, to make the
track come in to the top right corner (1 o clock). rather than as they
do now: from right side (3 o clock).

TX2 i'll have to move to the right somewhat...

[Richard Wilbur]

On Wed, Aug 23, 2017 at 5:27 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
damn. i just noticed: the via transition here is at 90 degrees.
i've been switching off except 1 layer at a time so didn't notice.
arse.
i'll need to shift all but the TX2 via set down a fixed amount so i
can get a second wiggle in the right-hand one one layer 1, to make the
track come in to the top right corner (1 o clock). rather than as they
do now: from right side (3 o clock).

Not necessarily bad on the same scale as you might think. Our board
is ~47mil thick while the copper is ~1mil thick, so when a signal
plunges into a via from top to bottom it's already making a 90 degree
turn into and out of the via.

I'm not criticizing your attempt to straighten out some corners we
have control over in the signal path, just pointing out that vias
themselves present the signal with a couple 90 degree turns.

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On Wed, Aug 30, 2017 at 9:34 PM, Richard Wilbur

Post by Richard Wilbur
On Wed, Aug 23, 2017 at 5:27 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
damn. i just noticed: the via transition here is at 90 degrees.
i've been switching off except 1 layer at a time so didn't notice.
arse.
i'll need to shift all but the TX2 via set down a fixed amount so i
can get a second wiggle in the right-hand one one layer 1, to make the
track come in to the top right corner (1 o clock). rather than as they
do now: from right side (3 o clock).

Not necessarily bad on the same scale as you might think. Our board
is ~47mil thick while the copper is ~1mil thick, so when a signal
plunges into a via from top to bottom it's already making a 90 degree
turn into and out of the via.
I'm not criticizing your attempt to straighten out some corners we
have control over in the signal path, just pointing out that vias
themselves present the signal with a couple 90 degree turns.

understood. which would be why they're best minimised and you're
also supposed to keep them as close together as possible.

i did however hear somewhere that it's really really bad to make via
tracks turn 180 back on themselves, and in the same vein it makes
sense not to turn them too much other than being a sort-of
"continuation" of "as if" they were on the same layer...

thx about the other responses.

l.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i
can shorten even more, there's definitely plenty of space there, big
gap.

Do you mean left end from the top of the board? (The first image I see shows the μHDMI connector end of the differential pairs.)

Post by Luke Kenneth Casson Leighton
2nd image, right end, this is where i've added intra-pair wiggles at
the 45 degree bends.

Do you mean right end from the top of the board? (The second image I see shows the SoC end of the HDMI differential pairs.)
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On Tue, Aug 29, 2017 at 7:12 PM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i
can shorten even more, there's definitely plenty of space there, big
gap.

Do you mean left end from the top of the board? (The first image I see shows the μHDMI connector end of the differential pairs.)

micro-hdmi connector is right end.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
2nd image, right end, this is where i've added intra-pair wiggles at
the 45 degree bends.

Do you mean right end from the top of the board? (The second image I see shows the SoC end of the HDMI differential pairs.)

SoC end of the HDMI traces is left end.

so.

http://lists.phcomp.co.uk/pipermail/arm-netbook/2017-August/014639.html

this is right end:
Loading Image...

this is left end:
Loading Image...

so.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i
can shorten even more, there's definitely plenty of space there, big
gap.

http://lists.phcomp.co.uk/pipermail/arm-netbook/attachments/20170822/a4632db6/attachment-0003.jpg

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
2nd image, right end, this is where i've added intra-pair wiggles at
the 45 degree bends.

http://lists.phcomp.co.uk/pipermail/arm-netbook/attachments/20170822/a4632db6/attachment-0002.jpg

l.

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[Richard Wilbur]

Luke,

Thank you ever so much for the clarification regarding perspective.

Comments inline below.

Post by Luke Kenneth Casson Leighton
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i
can shorten even more, there's definitely plenty of space there, big
gap.

Shortening CX and TX0 is fine but I would cramp any of the clearances to make it happen. On the other hand, if you were to put them into a 45° bend from south to southeast a little sooner, we would probably have enough room to adjust the ground shield trace on the southwest and west to abide by our 15mil differential trace to "anything not in the same pair" clearance (specifically to HTXCN).

Post by Luke Kenneth Casson Leighton
2nd image, right end, this is where i've added intra-pair wiggles at
the 45 degree bends. i can't get away with a proper 4-turn using 45
degrees, PADS goes "nope that's too short a trace, i'm gonna assume
you want a straight line instead" - there's probably an option
somewhere for that but i've not found it. alternatively i can add in
a (curvy) accordion....

I agree. If you don't have enough room to make a trace facet length >= 1.5 * trace width then I would also resort to an arc (curve). (Which for 5mil wide traces suggests minimum facet length of 7.5mil.)

Post by Luke Kenneth Casson Leighton
anyway those wiggles are done by hand, some of them aren't pretty but
in mil those traces are now nearly all to within 0.01 mil. i cheat a
little and have made some of the corners in places a very very tiny
arc, where you get better fine-grain control over the amount it takes
off.

Well done.

Post by Luke Kenneth Casson Leighton
HTXCN just before the diff-pair vias at the end i'm a little concerned
about, it looks a bit too... sharp-angled to make me feel totally
comfortable... not a lot of space... i tried a single wiggle and it
went too far away from HTXCP for me to feel happy about it.... put in
two much smaller wiggles instead...
GND i'll remove as the absolute last thing.

Sounds great. Only really want to remove the ground traces that can't comply with the 15mil clearance between differential pair and anything not in the same pair.
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Post by Richard Wilbur
Shortening CX and TX0 is fine but I would cramp any of the clearances to make it happen.

Sorry for any misconceptions. I meant to say:

"Shortening CX and TX0 is fine but I would not cramp any of the clearances to make it happen."
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[Luke Kenneth Casson Leighton]

On Wed, Aug 30, 2017 at 2:14 AM, Richard Wilbur

Post by Richard Wilbur

Post by Richard Wilbur
Shortening CX and TX0 is fine but I would cramp any of the clearances to make it happen.

"Shortening CX and TX0 is fine but I would not cramp any of the clearances to make it happen."

ah! luckily that can't be done anyway :)

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On Wed, Aug 30, 2017 at 1:54 AM, Richard Wilbur

Post by Richard Wilbur
Luke,
Thank you ever so much for the clarification regarding perspective.
Comments inline below.

Post by Luke Kenneth Casson Leighton
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i
can shorten even more, there's definitely plenty of space there, big
gap.

Shortening CX and TX0 is fine but I would cramp any
of the clearances to make it happen.

there aren't any!! the GND separation vias see to that (attached).
no there's not enough room to move those GND vias *in between* the
VIAs, they need to be below, unfortunately. that means the diffpairs
need to curve _round_ them (to the SW slightly). oops.

actually it just occurred to me that i could move the HXT?P vias over
by another.... 10-15 mil or so, which would mean that the
corresponding HXT?N traces would be able to go straight (directly
south) instead of SW, S then SE.

phrrrrddhh :)

Post by Richard Wilbur
On the other hand, if you were to put them into a 45°
bend from south to southeast a little sooner,
we would probably have enough room to adjust the ground shield
trace on the southwest and west to abide by our 15mil differential
trace to "anything not in the same pair" clearance (specifically to HTXCN).

well, unless i add a flood-exclusion zone (thoughts on that?)
anything W or SW of HTXCN is going to get flood-filled with GND.

or... i _could_ just put in a copper-to-diffpair Design Rule of "15
mil" clearance - that would keep the flood-fill away.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
anyway those wiggles are done by hand, some of them aren't pretty but
in mil those traces are now nearly all to within 0.01 mil. i cheat a
little and have made some of the corners in places a very very tiny
arc, where you get better fine-grain control over the amount it takes
off.

Well done.

... i'm getting used to it....

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
HTXCN just before the diff-pair vias at the end i'm a little concerned
about, it looks a bit too... sharp-angled to make me feel totally
comfortable... not a lot of space... i tried a single wiggle and it
went too far away from HTXCP for me to feel happy about it.... put in
two much smaller wiggles instead...
GND i'll remove as the absolute last thing.

Sounds great. Only really want to remove the ground traces
that can't comply with the 15mil clearance between differential pair and anything not in the same pair.

marked in this image, i was planning to remove the GND traces that
are marked with red dots.... but only after all's done because
currently they help keep the inter-pair separation.

does that sound sensible?

l.

[Richard Wilbur]

Sent from my iPhone

Post by Luke Kenneth Casson Leighton
On Wed, Aug 30, 2017 at 1:54 AM, Richard Wilbur
there aren't any!! the GND separation vias see to that (attached).
no there's not enough room to move those GND vias *in between* the
VIAs, they need to be below, unfortunately. that means the diffpairs
need to curve _round_ them (to the SW slightly). oops.
actually it just occurred to me that i could move the HXT?P vias over
by another.... 10-15 mil or so, which would mean that the
corresponding HXT?N traces would be able to go straight (directly
south) instead of SW, S then SE.

Which is an elegant way of doing some intra-pair (within the pair) skew compensation--by avoiding some the sources of skew to begin with. Sounds like a fine idea!

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
On the other hand, if you were to put them into a 45°
bend from south to southeast a little sooner,
we would probably have enough room to adjust the ground shield
trace on the southwest and west to abide by our 15mil differential
trace to "anything not in the same pair" clearance (specifically to HTXCN).

well, unless i add a flood-exclusion zone (thoughts on that?)
anything W or SW of HTXCN is going to get flood-filled with GND.

Flood-exclusion zone is just the ticket if you don't have a more flexible way. In this case it would increase the maintenance costs (time and effort) of the differential pair clearance to other circuits because it has to be manually checked and moved when needed.

Post by Luke Kenneth Casson Leighton
or... i _could_ just put in a copper-to-diffpair Design Rule of "15
mil" clearance - that would keep the flood-fill away.

I think this is the most maintainable solution.

[…]

Post by Luke Kenneth Casson Leighton
... i'm getting used to it....

"Practice makes easy."

[…]

Post by Luke Kenneth Casson Leighton
marked in this image, i was planning to remove the GND traces that
are marked with red dots.... but only after all's done because
currently they help keep the inter-pair separation.
does that sound sensible?

Eminently so!
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[Luke Kenneth Casson Leighton]

On Wed, Aug 30, 2017 at 7:18 AM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
actually it just occurred to me that i could move the HXT?P vias over
by another.... 10-15 mil or so, which would mean that the
corresponding HXT?N traces would be able to go straight (directly
south) instead of SW, S then SE.

Which is an elegant way of doing some intra-pair (within the pair)
skew compensation--by avoiding some the sources of skew
to begin with. Sounds like a fine idea!

mrhm grumble i have to redo those nice length-matchings.... agaaainn aaargh :)

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
or... i _could_ just put in a copper-to-diffpair Design Rule of "15
mil" clearance - that would keep the flood-fill away.

I think this is the most maintainable solution.

ok attached is the result of doing that. layer 1 just after the SoC
the "surround" on the vias is well over 15mil away, on *all* layers...
including GND. all VIAs are now avoided by the specified 15mil.

... seems a bit much, to me....

Post by Richard Wilbur
[
]

Post by Luke Kenneth Casson Leighton
... i'm getting used to it....

"Practice makes easy."
[
]

Post by Luke Kenneth Casson Leighton
marked in this image, i was planning to remove the GND traces that
are marked with red dots.... but only after all's done because
currently they help keep the inter-pair separation.
does that sound sensible?

Eminently so!

awesome.

[Richard Wilbur]

On Wed, Aug 30, 2017 at 4:01 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Wed, Aug 30, 2017 at 7:18 AM, Richard Wilbur

[...]

Post by Luke Kenneth Casson Leighton
mrhm grumble i have to redo those nice length-matchings.... agaaainn aaargh :)

I feel your pain. (I don't know whether this helps, but I've heard it
is for a good cause.;>)

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
or... i _could_ just put in a copper-to-diffpair Design Rule of "15
mil" clearance - that would keep the flood-fill away.

I think this is the most maintainable solution.

ok attached is the result of doing that. layer 1 just after the SoC
the "surround" on the vias is well over 15mil away, on *all* layers...
including GND. all VIAs are now avoided by the specified 15mil.
... seems a bit much, to me....

This is an attempt to maintain the impedance of the differential pairs
to ground which helps reduce the common mode signal (which will
radiate as EMI). With re-reading I noticed that the same document
from TI ("HDMI Design Guide") which recommends the clearance between
differential traces and any copper not a part of that same
differential pair be d >= 3s [1] also mentions in the summary of
routing guidelines some geometry recommendations among which is d > 2s
[2]. In doing some more reading on the subject, a TI High-Frequency
Analog design seminar slide mentions that it is common to put ground
planes along both sides of the microstrip differential pair but at a
larger distance than we have room to accommodate.(width > spacing, d >
2w)[3]

I believe we can abide by all of these constraints at d = 3s. Thus my
recommendation to move ground shields on the outside of the pairs to
15mil away from the closest pair and remove the ground shields between
the pairs because that will constitute 15mil spacing between pairs.

The seminar notes also suggest vias tying the ground in the signal
layer to the ground plane below the differential pair at least every
100mil along the signal path--quite a fence[3]. Obviously, we have to
accommodate the signals on other layers, as well.

The images as I received them were named:
received saved as
----------- -------------
Untitled3.jpg eoma68_a20_275b_connector_bot.jpg
Untitled2.jpg eoma68_a20_275b_processor_top.jpg
Untitled1.jpg eoma68_a20_275b_processor_bot.jpg
Untitled4.jpg eoma68_a20_275b_processor_gnd.jpg

What I notice in eoma68_a20_275b_connector_bot.jpg is that the ground
shield traces and ground vias which violate the 15mil
differential-pair-to-anything-else clearance stick out noticeably from
the ground fill. For the vias on the edge of the ground fill, one
possible solution would be to sneak them back inside the ground fill.
For ground vias that we need to be closer to the differential pair
traces or shouldn't move for other reasons (lack of space), can we
remove the via pad on the layer where they violate the clearance (in
this case layer 6)? That would minimize the coupling without changing
the connection between other ground layers.

In eoma68_a20_275b_processor_top.jpg, what I see looks good. I like
the curves on XN traces and angles on XP since the curves minimize
length to make a turn this also reduces the amount of intra-pair skew
(and thus how much compensation is required). I notice HTX2N didn't
get the same treatment. Is that because HTX2P makes an extra turn on
its way to the via?

In regard to eoma68_a20_275b_processor_bot.jpg I notice that Toradex
mentions spacing of parallel traces containing the same signal should
be >= 4 * trace width.[4] (For us that would be 4*5mil = 20mil.)
Thus all their pictures of intra-pair skew compensation don't have
parallel sections (unless they are very short like the tricks in
figure 31[5]):
_ _ _
\_/ \_/

or
_ _
_/ \_/ \_

instead of
_ _
\ /
| | <---parallel sections of same signal
\_/

They reserve parallel sections of same signal for large meanders
involved in inter-pair (between pairs) skew compensation.

I would try and move the bottom ground shield trace (and associated
fence vias) down 1mil so that the trace attains the 15mil clearance
with HTXCN.

Again, the ground vias and ground shield traces that are closer than
15mil to differential traces and can be moved to respect that boundary
would help improve the symmetry and keep the impedance up.

Specifically, the ground shield trace just north of the signal vias
which land the signals on layer 6, could move up parallel with the
north edge of the adjacent ground fill. Likewise the ground shield
trace on the west side of HTXCN could move even with the edge of the
ground fill on that side.

My name for eoma68_a20_275b_processor_gnd.jpg is a hypothesis as to
what I guess this is a picture of--one of the ground planes over the
top layer adjacent to the processor where the signal vias carry the
signal from top to bottom. Is that a correct hypothesis?

The keep outs look good from a signal impedance standpoint. It looks
like there is no pad on this layer (ground?) on the vias and the 15mil
clearance rule is having the expected effect. What did this part of
this layer look like before we instituted the 15mil clearance rule?
What clearance did we have before? Specifically, did we already have
a hole extending over all the signal vias' keep outs or were there
fingers of ground that made it between (preferably connecting north to
south)?

I don't especially like making such a large hole in the ground plane.
If it were only one of two ground planes with that hole I wouldn't
worry about it at all. This is both planes plus the power plane. So
let's consider it for a moment. Please correct any errors of fact or
perspective, below.
1. Each HDMI differential signal via is composed of a 6mil diameter
plated-through hole and pads on appropriate layers.
2. The clearance imposes a 15mil radius around the hole = 36mil void
in non-signal layer. (This then happens in power and both ground
planes.)
3. The return current (from common mode signal) wants to follow the
signal in relatively low impedance back to the signal source/driver
which implies a power or ground pin of the driver close to the signal
pin. Where are the power and ground pins on the SoC relative to the
HDMI signal pins? Does the SoC have both positive and negative supply
connections (e.g. +3.3V, -3.3V)? Are any of the pins suggestively
named such as: VHDMI+, VHDMI- or VDIFF+, VDIFF-?
4. The return current will detour as needed (but it raises the
impedance of the path). Probably want to keep the detours down to
~200mil.
5. Where on ground and power planes is the power flow most apparent?
(Are we blocking the direct path for any high-power flow? Where are
the power sources?[voltage convertors/regulators] Where are the power
sinks?[users of power: SoC, etc.])

References:

[1] TI HDMI, p. 5.2
[2] TI HDMI, p. 8, #10
[3] TI Analog, p. 14, beware: they label dimensions differently
[4] Toradex, page 17, section 6.2
[5] Toradex, page 25, figure 31


Bibliography:

Texas Instruments (TI HDMI): "HDMI Design Guide", High-Speed
Interface Products, June 2007,
http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-138-01-00-00-10-65-80/Texas-Instruments-HDMI-Design-Guide.pdf

Texas Instruments (TI Analog): "Section 5: High Speed PCB Layout
Techniques", High Speed Analog Design and Application Seminar, Date?,
http://www.ti.com/lit/ml/slyp173/slyp173.pdf

Toradex: "Layout Design Guide", v1.0, 14 April 2015,
http://docs.toradex.com/102492-layout-design-guide.pdf

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[Luke Kenneth Casson Leighton]

http://rhombus-tech.net/allwinner_a10/news/

ok so after the successful DC3 test this is the last final check
before sending the gerbers off to the factory for pre-production
prototyping. in the end i used a "keepout" area on both layers 1 and
3, drawn by hand, to ensure that no GND flooding gets near the HDMI
traces on layers 1 and 6. l'm including layer 3 as an example of how
the group of HDMI vias that come just out of the A20 punch a large
hole: GND-flooded layers 2 and 5 as well as 4 (power plane) will also
look like that.

richard if you want to zoom in on those pictures you should be able to
click on them in a browser, then expand them: they're actually around
2,500 pixels wide, i just asked them to be displayed in that HTML page
as only 1024 otherwise they wouldn't fit :)

you can see i removed the GND traces in between, and generally kept
everything except VIAs away from them. it's not perfect but thanks to
your help i'm pretty happy with it. if there's nothing major i want
to send this off.

l.

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[Richard Wilbur]

On Sat, Sep 16, 2017 at 8:23 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
http://rhombus-tech.net/allwinner_a10/news/
ok so after the successful DC3 test this is the last final check
before sending the gerbers off to the factory for pre-production
prototyping.

3*Cheer!

Post by Luke Kenneth Casson Leighton
in the end i used a "keepout" area on both layers 1 and
3, drawn by hand, to ensure that no GND flooding gets near the HDMI
traces on layers 1 and 6.

"keepout" on layers 1 and 6, right? Not a bad idea, especially since
it allows the situations at both ends of the traces to avoid design
rule check (DRC) failures because we have copper that has to be closer
than 15mil there.

Post by Luke Kenneth Casson Leighton
l'm including layer 3 as an example of how
the group of HDMI vias that come just out of the A20 punch a large
hole: GND-flooded layers 2 and 5 as well as 4 (power plane) will also
look like that.

Could you put a similar snapshot of layers 2, 4, 5 on hands.com (or
wherever you think appropriate)? I'm interested to see what
holes/voids and connections the power and ground planes have.

What are the names of the power pins on the A20? What voltages do you
supply it? (Are any of them Vdiff+/-, e.g?) I'm interested in
tracking down the power supply pins for the differential HDMI signals
as that is where our return path for common-mode signal has to go.

I've read a little (not nearly as much as I'd like, but I lack time)
about using a taper to match impedance differences while minimizing
the reflection coefficient.[*] I'm thinking we can use it at both
ends of this layout to great advantage. We taper from 5mil clearance
around the A20 on layer 1 to 15mil clearance on layer 6. Later we
taper from 15mil clearance to whatever the closest copper is at the
ESD and connector lands.

Is the closest copper on layer 1, around the A20, 5mil from the HDMI
differential signals?

What is the distance to the closest copper to the HDMI signals at the ESD lands?

What is the distance to the closest copper to the HDMI signals at the
connector lands?

(I'm guessing in both cases it is likely the neighbouring lands. Is
that correct?)

What is the minimum frequency we will be running the HDMI at? (With
version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate
on each data line. Thus I would expect good edges if we design for
harmonics of 34GHz.;>)

What is the vertical distance from layer to layer in our board stack?

The idea is we can taper the keepouts on our signal vias near the A20
by the layer and avoid such an abrupt change from layer 1 to layer 6.

Likewise, we can change the geometry of the keepout as we approach the
ESD lands and finally the connector to likewise ease the transition.

Post by Luke Kenneth Casson Leighton
richard if you want to zoom in on those pictures you should be able to
click on them in a browser, then expand them: they're actually around
2,500 pixels wide, i just asked them to be displayed in that HTML page
as only 1024 otherwise they wouldn't fit :)

Thank you. I am enjoying the views you posted.

Post by Luke Kenneth Casson Leighton
you can see i removed the GND traces in between, and generally kept
everything except VIAs away from them. it's not perfect but thanks to
your help i'm pretty happy with it. if there's nothing major i want
to send this off.

There is one place in layer 6 where the space between the CLK pair and
the adjacent data pair looks like it exceeds 35mil for a non-trivial
distance. I think we could safely reintroduce a ground trace
connecting the 2 or 3 vias in that space and thus keep the environment
close to 15mil from differential trace to either ground or
neighbouring signal.

I'm not sure which of the gray dots are vias and which are not. Some
of the vias might be able to sneak back into the ground-fill (out of
the 15mil differential line clearance).

Reference:

[*] https://electronics.stackexchange.com/questions/84098/a-transmission-line-with-continuously-varying-impedance-how-would-reflection-oc
https://www.microwaves101.com/encyclopedias/klopfenstein-taper

[Luke Kenneth Casson Leighton]

On Tue, Sep 19, 2017 at 11:26 PM, Richard Wilbur

Post by Richard Wilbur
On Sat, Sep 16, 2017 at 8:23 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
http://rhombus-tech.net/allwinner_a10/news/
ok so after the successful DC3 test this is the last final check
before sending the gerbers off to the factory for pre-production
prototyping.

3*Cheer!

:)

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
in the end i used a "keepout" area on both layers 1 and
3, drawn by hand, to ensure that no GND flooding gets near the HDMI
traces on layers 1 and 6.

"keepout" on layers 1 and 6, right?

yehyeh. only where needed. not "cut-through to all layers"

Post by Richard Wilbur
Not a bad idea, especially since
it allows the situations at both ends of the traces to avoid design
rule check (DRC) failures because we have copper that has to be closer
than 15mil there.

yehyeh

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
l'm including layer 3 as an example of how
the group of HDMI vias that come just out of the A20 punch a large
hole: GND-flooded layers 2 and 5 as well as 4 (power plane) will also
look like that.

Could you put a similar snapshot of layers 2, 4, 5 on hands.com (or
wherever you think appropriate)?

they're exactly the same as what you see for layer 3.... except
entirely full. ok that's not actually true (i just checked) - do a
page-refresh on the URL i just added layer 4 image)

Post by Richard Wilbur
I'm interested to see what
holes/voids and connections the power and ground planes have.

there are *no* connections on the GND planes. the power plane (and
GND layers) interestingly have done a full surround on the HDMI vias.
remember i had to separate them by an unusual distance.

Post by Richard Wilbur
What are the names of the power pins on the A20? What voltages do you
supply it?

1.1, 1.25, 2.5 and 3.3v.

Post by Richard Wilbur
(Are any of them Vdiff+/-, e.g?)

no.

Post by Richard Wilbur
I'm interested in
tracking down the power supply pins for the differential HDMI signals
as that is where our return path for common-mode signal has to go.

there's no specific power pin for HDMI. the GND pins are grouped in
with a whole stack of other GND pins, there's absolutely no way it's
practical to get a special GND plane to it: the board is extremely
full already.

Post by Richard Wilbur
I've read a little (not nearly as much as I'd like, but I lack time)
about using a taper to match impedance differences while minimizing
the reflection coefficient.[*] I'm thinking we can use it at both
ends of this layout to great advantage. We taper from 5mil clearance
around the A20 on layer 1 to 15mil clearance on layer 6. Later we
taper from 15mil clearance to whatever the closest copper is at the
ESD and connector lands.

that's something that it would be helpful to have a rough diagram,
even if it's hand-drawn [but see below: i think i understand it]

Post by Richard Wilbur
Is the closest copper on layer 1, around the A20, 5mil from the HDMI
differential signals?

yes. everything's 5 mil design rule.

Post by Richard Wilbur
What is the distance to the closest copper to the HDMI signals at the ESD lands?

5 mil

Post by Richard Wilbur
What is the distance to the closest copper to the HDMI signals at the
connector lands?

5 mil

Post by Richard Wilbur
(I'm guessing in both cases it is likely the neighbouring lands. Is
that correct?)
What is the minimum frequency we will be running the HDMI at? (With
version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate
on each data line. Thus I would expect good edges if we design for
harmonics of 34GHz.;>)

:) 1920x1080p60. honestly though if it works at 1280x720p60 i'll be happy.

Post by Richard Wilbur
What is the vertical distance from layer to layer in our board stack?

it's a 6 layer 1.2mm PCB. if i have actually set the design
parameters right (rather than just telling the factory manually) then
the substrates are 1.35mil and the dielectrics 10mil

Post by Richard Wilbur
The idea is we can taper the keepouts on our signal vias near the A20
by the layer and avoid such an abrupt change from layer 1 to layer 6.

i would very much like to have used layer 3 instead of layer 6 for
the HDMI signals long straightaway but it is too late now

Post by Richard Wilbur
Likewise, we can change the geometry of the keepout as we approach the
ESD lands and finally the connector to likewise ease the transition.

okaaaay i think i understand what you mean.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
richard if you want to zoom in on those pictures you should be able to
click on them in a browser, then expand them: they're actually around
2,500 pixels wide, i just asked them to be displayed in that HTML page
as only 1024 otherwise they wouldn't fit :)

Thank you. I am enjoying the views you posted.

:)

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
you can see i removed the GND traces in between, and generally kept
everything except VIAs away from them. it's not perfect but thanks to
your help i'm pretty happy with it. if there's nothing major i want
to send this off.

There is one place in layer 6 where the space between the CLK pair and
the adjacent data pair looks like it exceeds 35mil for a non-trivial
distance. I think we could safely reintroduce a ground trace
connecting the 2 or 3 vias in that space and thus keep the environment
close to 15mil from differential trace to either ground or
neighbouring signal.

good call. i know exactly where you mean. refresh URL and see new image.

http://rhombus-tech.net/allwinner_a10/news/

ok i did the taper at the DC3 connector end, and i think i got it
reasonably ok at the A20 end. haven't run flood-fill. A20 end is a
bit of a mess, bit unavoidable. left side is ok. right side...
because of the immediate turn and the TX2 line...

Post by Richard Wilbur
I'm not sure which of the gray dots are vias and which are not. Some
of the vias might be able to sneak back into the ground-fill (out of
the 15mil differential line clearance).

they're all vias with the exception of the 2 we previously identified
as being "centre of component indicator". which.... i don't believe
are actually in the images because i specifically selected "one and
only one layer" in each.

you probably saw those dots because previous images included "all
layers". the dots are on... some special layers, don't know which
ones.

ok.

so. i really want to wrap this up, and get the gerbers out.

loootta work... :)

l.

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[Luke Kenneth Casson Leighton]

richard re image, yes yellow vias moved as far as possible, actually
deleted the top right one as there's components (ESD) in the way on
layer 1.

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[Richard Wilbur]

I have a question about one of the traces: In the layout picture it appears that something resembling a via coincides with HTX1P following the second wiggle after the trace turns NE. If it is a via, what is it doing there? If not, what is it?

I would recommend if you want to be able to solder or desolder by hand the μHDMI connector to/from the board that you use thermal relief (multiple spokes emanating from the land) when connecting ACIN-5V to pin 19. On the other hand, this solid layout does make a lower impedance connection for power and should work fine in the surface-mount oven for soldering as long as you have solder resist covering the trace outside the ESD land for pin 19.

Of course, hopefully you never have need of soldering or desoldering the μHDMI connector by hand. Looks best left to the oven.
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[Luke Kenneth Casson Leighton]

On Wed, Aug 30, 2017 at 7:59 AM, Richard Wilbur

Post by Richard Wilbur
I have a question about one of the traces: In the layout picture it appears that something resembling a via coincides with HTX1P following the second wiggle after the trace turns NE. If it is a via, what is it doing there? If not, what is it?

you've lost me, sorry. i don't know if you have access to an image
editor but an arrow pointing would help - i know you're using an
iphone so that might be a leetle awwkward...

Post by Richard Wilbur
Of course, hopefully you never have need of soldering or desoldering the μHDMI connector by hand. Looks best left to the oven.

yyeah this connector is a bitch to take off by hand. the heatgun
literally melts the plastic inside the case and that's it, it's done -
in the bin. with the added risk that it can strip off the pads on its
way up.

then when you try and put a replacement on, that melts too, the pins
move off the same plane and it's game over for *that* connector, too.

this is why we'll be doing a test run of some low-cost 2-layer PCBs
(1in x 1in) just with the DC3 land pattern and some test jumpers,
which will go through the oven to make sure that the DC3 actually sits
down and all pins connect to their pads.

lot less risky than $USD 2,000 for complete PCBs only to find that
after 5-8 weeks yet another footprint layout doesn't work.....

l.

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[Richard Wilbur]

I'm working on replies to both of your last two messages and hope to send them in the next 6-12 hours. I'm trying to finish some other stuff while I have sunlight.
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[Richard Wilbur]

On Wed, Aug 30, 2017 at 4:07 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Wed, Aug 30, 2017 at 7:59 AM, Richard Wilbur

Post by Richard Wilbur
I have a question about one of the traces: In the layout picture it appears that something resembling a via coincides with HTX1P following the second wiggle after the trace turns NE. If it is a via, what is it doing there? If not, what is it?

you've lost me, sorry. i don't know if you have access to an image
editor but an arrow pointing would help - i know you're using an
iphone so that might be a leetle awwkward...

Borrowing my wife's laptop I used the bundled Paint program to scratch
some marks on the image from your wiggles progress message. What I'm
referring to has been in the layout pictures for a while longer than
the image I used to note it and I was curious but had bigger fish to
fry.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Of course, hopefully you never have need of soldering or desoldering the ÎŒHDMI connector by hand. Looks best left to the oven.

[...]

Post by Luke Kenneth Casson Leighton
this is why we'll be doing a test run of some low-cost 2-layer PCBs
(1in x 1in) just with the DC3 land pattern and some test jumpers,
which will go through the oven to make sure that the DC3 actually sits
down and all pins connect to their pads.
lot less risky than $USD 2,000 for complete PCBs only to find that
after 5-8 weeks yet another footprint layout doesn't work.....

Good plan.

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

Post by Richard Wilbur
On Wed, Aug 30, 2017 at 4:07 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Wed, Aug 30, 2017 at 7:59 AM, Richard Wilbur

Post by Richard Wilbur
I have a question about one of the traces: In the layout picture it appears that something resembling a via coincides with HTX1P following the second wiggle after the trace turns NE. If it is a via, what is it doing there? If not, what is it?

you've lost me, sorry. i don't know if you have access to an image
editor but an arrow pointing would help - i know you're using an
iphone so that might be a leetle awwkward...

Borrowing my wife's laptop I used the bundled Paint program to scratch
some marks on the image from your wiggles progress message.

*grin*

Post by Richard Wilbur
What I'm
referring to has been in the layout pictures for a while longer than
the image I used to note it and I was curious but had bigger fish to
fry.

ah! ok, i know what it is - it's the centre mark of a big pad on the
layer below. nice feature (gets in the way, here) - the centre of a
pad is marked with a to-scale circle that is displayed on all layers.
in this case, as that's a 1206 component the circle is huuuge.... and
coincidentally the same size as a VIA :)

so... can be safely ignored.

l.

[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
ah! ok, i know what it is - it's the centre mark of a big pad on the
layer below. nice feature (gets in the way, here) - the centre of a
pad is marked with a to-scale circle that is displayed on all layers.
in this case, as that's a 1206 component the circle is huuuge.... and
coincidentally the same size as a VIA :)
so... can be safely ignored.

Thank you for setting my mind at ease.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
SATA was on a very preliminary version of EOMA68. it was cut a long time ago.

Sorry for bringing up old news.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Regarding SD0: To what interface does it belong? What is the maximum data rate on this line?

MicroSD card reading (and other SD/MMC / SDIO compatible interfaces).
i *think* it's a max datarate of 50mhz....

Sounds like SD0 is high-frequency single-ended so it might warrant a ground shield trace--if there's room. But I would rather maintain the 15mil differential pair trace to any other trace spacing because I'm guessing the coupling to differential pairs will be small. (It is not parallel to differential signals for a significant distance, is it?)
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[Luke Kenneth Casson Leighton]

On Wed, Aug 23, 2017 at 8:04 PM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
SATA was on a very preliminary version of EOMA68. it was cut a long time ago.

Sorry for bringing up old news.

ey no problem it's all interesting stuff

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
MicroSD card reading (and other SD/MMC / SDIO compatible interfaces).
i *think* it's a max datarate of 50mhz....

Sounds like SD0 is high-frequency single-ended
so it might warrant a ground shield trace--if there's room.

there is... just!

Post by Richard Wilbur
But I would rather maintain the 15mil differential pair trace to any
other trace spacing because I'm guessing the coupling to
differential pairs will be small. (It is not parallel to differential
signals for a significant distance, is it?)

nono - they run round the back of the vias (attached) - yellow, 6 lines.

l.

[Richard Wilbur]

On Wed, Aug 9, 2017 at 7:23 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
next set...
wiggles.jpg is the layer 6 length-matching area: HX2N/P is the one
that's the longest, it snakes back on itself. i length-matched all 3
signal pairs to 56.413, and left the CK lines at 57.134 just to give
the tiniest bit of delay (TI recommendations iirc).

Very nicely done! 57.134mm - 56.413mm = 721um
=> T(delay) = 721um / 150um/ps = 4.8ps

That is a very tiny delay! Now that we have achieved such close
synchronization, I'm suggesting we go for the next goal where we
design a certain amount of inter-pair skew into the layout for
purposes of lowering the strength of our synchronized pulsing data
lines to a more diffuse chatter.

Post by Luke Kenneth Casson Leighton
no - not even enough space to do 5.1mil / 5.0 clearance... just... too much.

I understand. We might end up with more room--see discussion below.

Post by Luke Kenneth Casson Leighton
the other images show the via'd portions, they're all either
symmetrical or perfectly length-matched to 0.001mm.

Again, they look nice.<div id="DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2"><br />
<table style="border-top: 1px solid #D3D4DE;">
<tr>
<td style="width: 55px; padding-top: 13px;"><a
href="http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail"
target="_blank"><img
src="Loading Image..."
alt="" width="46" height="29" style="width: 46px; height: 29px;"
/></a></td>
<td style="width: 470px; padding-top: 12px; color: #41424e;
font-size: 13px; font-family: Arial, Helvetica, sans-serif;
line-height: 18px;">Virus-free. <a
href="http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail"
target="_blank" style="color: #4453ea;">www.avg.com</a>
</td>
</tr>
</table><a href="#DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2" width="1"
height="1"></a></div>

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[Luke Kenneth Casson Leighton]

On Fri, Aug 11, 2017 at 12:37 AM, Richard Wilbur

Post by Richard Wilbur
On Wed, Aug 9, 2017 at 7:23 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
next set...
wiggles.jpg is the layer 6 length-matching area: HX2N/P is the one
that's the longest, it snakes back on itself. i length-matched all 3
signal pairs to 56.413, and left the CK lines at 57.134 just to give
the tiniest bit of delay (TI recommendations iirc).

Very nicely done! 57.134mm - 56.413mm = 721um
=> T(delay) = 721um / 150um/ps = 4.8ps
That is a very tiny delay!

ooooOoo :)

Post by Richard Wilbur
Now that we have achieved such close
synchronization, I'm suggesting we go for the next goal where we
design a certain amount of inter-pair skew into the layout for
purposes of lowering the strength of our synchronized pulsing data
lines to a more diffuse chatter.

*deep breath*.... aaaaaaaa! :)

well.... that actually happens for the majority of the length in the
middle (starting layer 6)

but.... if i simply *take out* the intermediary wiggles on layer 6....

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
no - not even enough space to do 5.1mil / 5.0 clearance... just... too much.

I understand. We might end up with more room--see discussion below.

which has probably been truncated...

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
the other images show the via'd portions, they're all either
symmetrical or perfectly length-matched to 0.001mm.

Again, they look nice.<div id="DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2">

whoops.... something melted there...

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[Luke Kenneth Casson Leighton]

ok richard, so what would you suggest for the amount of skew to be added?

l.

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[Richard Wilbur]

On Fri, Aug 11, 2017 at 1:36 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
ok richard, so what would you suggest for the amount of skew to be added?

Sorry about the HTML that snuck into that last message! I deleted a
similar egregious amount of off-color HTML in the previous message
that must be coming from one of my E-mail clients when I instructed it
to reply. (I just saw it again on this message. Turns out the free
anti-virus software from AVG on this M$ windows machine was configured
to add an E-mail signature which looks like it was basically an HTML
advertisement with URL. I disabled it so I hope to not see any more.)

My earlier message from yesterday opens the discussion of designing a
certain amount of inter-pair skew into the HDMI signals. Before I
give a more definitive recommendation it would be useful to know the
pair lengths of each of the 3 HDMI data pairs HTX0, HTX1, HTX2, and
the clock pair length HTXC before you added inter-pair skew
compensation.

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[Luke Kenneth Casson Leighton]

On Fri, Aug 11, 2017 at 4:30 PM, Richard Wilbur

Post by Richard Wilbur
My earlier message from yesterday opens the discussion of designing a
certain amount of inter-pair skew into the HDMI signals. Before I
give a more definitive recommendation it would be useful to know the
pair lengths of each of the 3 HDMI data pairs HTX0, HTX1, HTX2, and
the clock pair length HTXC before you added inter-pair skew
compensation.

previous message. look through logs or archives. clock's 57.135.
HTX2 was something like 49. others in between.

l.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Fri, Aug 11, 2017 at 12:37 AM, Richard Wilbur

Post by Richard Wilbur
On Wed, Aug 9, 2017 at 7:23 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
next set...
wiggles.jpg is the layer 6 length-matching area: HX2N/P is the one
that's the longest, it snakes back on itself. i length-matched all 3
signal pairs to 56.413, and left the CK lines at 57.134 just to give
the tiniest bit of delay (TI recommendations iirc).

Very nicely done! 57.134mm - 56.413mm = 721um
=> T(delay) = 721um / 150um/ps = 4.8ps
That is a very tiny delay!

I would need to do more research to make a meaningful recommendation. Sorry for bringing up a topic I wasn't prepared to discuss intelligently. Let's go with what you've done.

According to my calculations you could get away without any inter-pair skew compensation on the board whatsoever and still meet the HDMI specification for the transmitter budget. What you have done regarding inter-pair skew compensation reserves nearly all of the transmitter inter-pair skew budget from the HDMI standard for the connector and the rest of the system. This will serve to accommodate less than optimal inter-pair skew imposed by the cable and/or receiver.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Now that we have achieved such close
synchronization, I'm suggesting we go for the next goal where we
design a certain amount of inter-pair skew into the layout for
purposes of lowering the strength of our synchronized pulsing data
lines to a more diffuse chatter.

*deep breath*.... aaaaaaaa! :)
well.... that actually happens for the majority of the length in the
middle (starting layer 6)
but.... if i simply *take out* the intermediary wiggles on layer 6....

Ill-founded proposal for which I don't presently have the time to improve.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
no - not even enough space to do 5.1mil / 5.0 clearance... just... too much.

I understand. We might end up with more room--see discussion below.

which has probably been truncated...

Turns out we don't have the room to change the trace width or spacing without having a deleterious effect on impedance.
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[Luke Kenneth Casson Leighton]

On Tue, Aug 15, 2017 at 12:08 AM, Richard Wilbur

Post by Richard Wilbur
I would need to do more research to make a
meaningful recommendation. Sorry for bringing up
a topic I wasn't prepared to discuss intelligently.
Let's go with what you've done.

hey this is all extremely worthwhile. it's me who is barely able to
follow along.

Post by Richard Wilbur
According to my calculations you could get away without
any inter-pair skew compensation on the board whatsoever
and still meet the HDMI specification for the transmitter budget.

ah ha!! that would be better, it's quite a mess to be honest.

Post by Richard Wilbur
What you have done regarding inter-pair skew compensation
reserves nearly all of the transmitter inter-pair skew budget
from the HDMI standard for the connector and the rest of the
system. This will serve to accommodate less than optimal
inter-pair skew imposed by the cable and/or receiver.

.... i'm translating this to mean "lose the large middle set
of wiggles on TX0, TX1 and TX2". they're bugging me anyway ("beauty" criteria)

plus, we know that the very first design.. i should open that up
shouldn't i... never had large wiggles and it worked fine. looking at
it now, the guy who designed it had all the vias coming out from the
CPU in a straight line, no diff-pair via considerations *at all*, ran
the CK lines right past *all* those vias, but, butbutbut, he put CK on
layer 6, TX0-2 on layer 3

i'm amazed it worked.

Post by Richard Wilbur
Turns out we don't have the room to change the trace width or spacing without having a deleterious effect on impedance.

blech :)

l.

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[Luke Kenneth Casson Leighton]

trying the images again (adding image/png to allowed attachment types)....

[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
okaay, so this is what i've managed for the outgoing vias (layer 1),
the two lengths are equal (to each other and including across all four
pairs) and the relative positions of each via are identical.

Very nicely done--especially considering how tight that space is. I like the way you snuck some extra length on the traces from the closer pins and with 45 degree bends no less.

Post by Luke Kenneth Casson Leighton
for layer 6.... faak it's tight on space down the bottom, so i simply
can't get anything but "turns" in. it'll have to go dead-straight
until the other end of the board, after the PMIC, where i'll then be
able to correct the length differences between the CLK pair and the
other pairs.

Since the digital portion of the receivers is built to specifically correlate up to 5 (out of 10) bit times of inter-pair skew (arrival time difference between differential pairs) for every pixel clock, you could think of building in some inter-pair skew as similar to spread-spectrum techniques which have been employed in communications to drop the energy peak on the carrier frequency and more recently on motherboard chipsets. The clock period for 340MHz is
T(Pixel) = 1/(pixel clock) = 1/(340MHz) = 2.94ns
wavelength = velocity * period = 150um/ps * 2940ps = 441mm = 17400mil
So half that period = 1470ps, which at the speed of propagation is ~ 220mm ~ 8700mil. So there is our inter-pair skew budget for the whole path: differential driver, IC lead wire, pin, PCB (the part we have design control of presently), connector, HDMI cable, connector, receiver PCB, pin, IC lead wire, receiver. I believe that if we reserve one-tenth of that inter-pair skew for our transmitter PCB, we should not be unduly stressing the budget and that amounts to ~ 22mm ~ 870mils. Interestingly this is Toradex' suggested limit for skew between clock and data. The HDMI standard restricts transmitters to
T(inter-pair skew) = 0.2 * T(pixel) = 2 * T(bit) = 588ps
=> Δl < v * Δt = 88.2mm ~= 3470mil

Post by Luke Kenneth Casson Leighton
richard you said that the difference between all pairs should be no
more than 100mil, right? but that clock should be a leetle bit
longer.

I did suggest we might work towards that as a goal based on Chrontel's recommendation, but now I'm giving the spread-spectrum idea more thought and thinking we might design some inter-pair skew into the system on purpose to reduce the amplitude of EM from the constructive interference of all those (painstakingly) phase-aligned transitions. So here is one strategy to implement what I was thinking (predicated on the spread between shortest and longest data pairs being less than 0.5 * L(bit)):
1. Shortest pair becomes our reference length.
2. Other two data pairs are routed different fractions of T(bit) longer than the reference pair.
3. Clock pair is routed a larger fraction of T(bit) longer.

Hence:
L(reference) = L(shortest data pair without inter-pair skew compensation)
T(bit) = 294ps
=> L(bit) = v * T(bit) = 150um/ps * 294ps = 44.1mm ~ 1740mil
Suppose we select fractions: 0.2, 0.3, 0.5(clock)
then we would make L(longer data pair) = L(reference) + 0.2 * L(bit)
L(longest data pair) = L(reference) + 0.3 * L(bit)
L(clock pair) = L(reference) + 0.5 * L(bit) = L(reference) + 22mm

I guess I should first ask what are the differential pair lengths before inter-pair skew corrections?

Post by Luke Kenneth Casson Leighton
CLK-pairs are 57.245 (i got them to within a thousandth of a mm!
57.245 and 57.24518 how jammy is that!!)

Now that is some great length matching! And intra-pair where it looks like it matters the most!

Post by Luke Kenneth Casson Leighton
HX2N/P are 49.something - a hell of a big difference. luckily that
one's on the outside edge so i can "wiggle" it a lot :)

The clock data difference is ~8mm ~ 310mil.

That's around an order of magnitude (factor of 10) smaller than the limit the HDMI standard imposes on transmitters and more than a factor of 2 smaller than Toradex' recommended limit.

Post by Luke Kenneth Casson Leighton
oh... i had another go at the USB pairs, after reading all that you
recommended i wasn't happy that there was skew (which i never noticed
before). the USB lines worked but there would have been quite a bit
of EM.

I must confess I hadn't looked at the USB traces but it sounds like a good thing. Which level of support are you providing?
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[Andrew Bolin]

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Also I'd personally not use curved wriggles. HF signals travel in a
straight direction. With curves they start diffracting and start
bouncing cross each other and might start to radiate or echo back.

mmmmm.... *stress*! anyone else feel the curves are "Bad"?

No. You've followed a bunch of very good advice about length matching,
impedance etc.
It looks like you've generally kept the pairs parallel through the curves,
which is great.

If you have an easy option in your software to switch from 45 degree
corners to smooth curves, I would do it - if there's not, don't worry.

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
If tight for space you can use 90% corners with a chamfered outer
edge. I suppose the chamfer acts like a mirror.

The chamfer is there for impedance reasons, it's not a mirror, and note
that a curve is preferred.
You also run the risk of manufacturing problems by doing the chamfer -
you're already at the minimum trace width, right?

As you've previously said, the old layout was further away from best
practices, and *it worked*.
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[Luke Kenneth Casson Leighton]

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On Fri, Aug 11, 2017 at 2:56 AM, Andrew Bolin

Post by Andrew Bolin

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
Also I'd personally not use curved wriggles. HF signals travel in a
straight direction. With curves they start diffracting and start
bouncing cross each other and might start to radiate or echo back.

mmmmm.... *stress*! anyone else feel the curves are "Bad"?

No. You've followed a bunch of very good advice about length matching,
impedance etc.
It looks like you've generally kept the pairs parallel through the curves,
which is great.
If you have an easy option in your software to switch from 45 degree
corners to smooth curves, I would do it - if there's not, don't worry.

i did those by hand using the "accordian" feature

Post by Andrew Bolin

Post by Luke Kenneth Casson Leighton

Post by m***@gmail.com
If tight for space you can use 90% corners with a chamfered outer
edge. I suppose the chamfer acts like a mirror.

The chamfer is there for impedance reasons, it's not a mirror, and note
that a curve is preferred.
You also run the risk of manufacturing problems by doing the chamfer -
you're already at the minimum trace width, right?

yehyeh

Post by Andrew Bolin
As you've previously said, the old layout was further away from best
practices, and *it worked*.

but it was done by someone else and it didn't use curves.

l

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