Discussion:
[Arm-netbook] New Risc-V fully free chip
Bill Kontos
2017-11-17 21:10:32 UTC
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Just noticed this:

https://bitbucket.org/casl/shakti_public/

Probably worth keeping it in mind for the next couple years.

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Luke Kenneth Casson Leighton
2017-11-19 03:44:19 UTC
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Post by Bill Kontos
https://bitbucket.org/casl/shakti_public/
yeh the same team that was mentioned last week. suggestions on how
to contact them appreciated.

l.

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zap
2017-11-19 04:20:47 UTC
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Post by Luke Kenneth Casson Leighton
Post by Bill Kontos
https://bitbucket.org/casl/shakti_public/
yeh the same team that was mentioned last week. suggestions on how
to contact them appreciated.
l.
The first version of the shakti processor aka the extremely low voltage
one, is of high interest to me. I am sure it is to Luke as well given
this is his project. :)

I hope that good things come from this.
Post by Luke Kenneth Casson Leighton
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Bill Kontos
2017-11-19 10:52:35 UTC
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On Sun, Nov 19, 2017 at 5:44 AM, Luke Kenneth Casson Leighton
Post by Luke Kenneth Casson Leighton
yeh the same team that was mentioned last week. suggestions on how
to contact them appreciated.
From that link:

IF YOU ARE INTERESTED IN A EARLY ACCESS TO THE C-CLASS (64-BIT) PLEASE
MAIL US AT: Madhusudan : gs dot madhusudan at cse dot iitm dot ac dot
in Neel Gala : neelgala at gmail dot com

C class

32 and 64 bit 3-8 stage in-order core aimed at 10 Mhz - 1 Ghz
controller requiremenets
Optional memory protection and MMU
Very low power static design varinats
Fault Tolerant variants for ISO26262 applications
IoT variants will have compressed/reduced ISA support
Optional FPU, VPU
Bus - AHB variants

To me it looks like the first one is too slow for general purpose
computing, we would need the absolute maximum configuration to make
something useful as a desktop chip. The I class is probably better
suited.

I class

64-bit, 1-8 core, 8+ stage out of order, aimed at 200 Mhz - 2 Ghz
industrial control / general purpose applications
Shared L2 cache, dual threading support, SIMD/VPU
BUS - Shakti NoC + AXI4


This is the HN discussion:

https://news.ycombinator.com/item?id=15684225

The lead architect of this project( username gsmadhusudan) has some
more comments about it:

Yes, we will update the C Class next month since our private line has
a lot of foundry specific code that needs to be removed. The I class
needs more work but the design is in place. It will also move to quad
issue and would be a Cortex A72/75 class core. More importantly the
basic slow IPs, UART, I2C, quad/Octal SPI, SDRAM controller, JTAG,
DMA, PLIC will be FPGA and silicon proven and production quality. Will
be very useful to other developers (non RISC-V also) as would the AXI
bus.

Cortex A72 is a pretty big core that just made it into a phone thermal
budget with the first generation 16nm finfet process. One example is
the kirin 950( found in the huawei Mate 8). From anandtech's review
here are 2 links about power consumption:

Loading Image...
Loading Image...

Full review here( and please don't ask me about non-free js on the
article): https://www.anandtech.com/show/9878/the-huawei-mate-8-review/3

Phones usually take around 3 watts tdp, so it looks like something of
this class could fit on an eoma68 card. Obviously the "optional
fpu-vpu" part remains a big question, while there also needs to be
someone who think they can sell a few million of these so they get
manufactured on a good enough node.

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Luke Kenneth Casson Leighton
2017-11-19 11:03:20 UTC
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Post by Bill Kontos
On Sun, Nov 19, 2017 at 5:44 AM, Luke Kenneth Casson Leighton
Post by Luke Kenneth Casson Leighton
yeh the same team that was mentioned last week. suggestions on how
to contact them appreciated.
thx bill

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r***@Safe-mail.net
2017-11-19 08:44:15 UTC
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-------- Original Message --------
From: Luke Kenneth Casson Leighton <***@lkcl.net>
Apparently from: arm-netbook-***@lists.phcomp.co.uk
To: Eco-Conscious Computing <arm-***@lists.phcomp.co.uk>
Subject: Re: [Arm-netbook] New Risc-V fully free chip
Date: Sun, 19 Nov 2017 03:44:19 +0000
Post by Luke Kenneth Casson Leighton
suggestions on how
to contact them appreciated.
Current Team Members:

Rahul Bodduna (***@gmail.com)
Neel Gala (***@gmail.com)
Arjun Menon (***@gmail.com)
G Vinod (***@gmail.com)
Abhinaya Agrawal (***@gmail.com)
G S Madhusudan (***@cse.iitm.ac.in, ***@macaque.in)
V. Kamakoti (***@cse.iitm.ac.in, ***@gmail.com)

For Queries/Collaboration/Feedback :

***@gmail.com
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Luke Kenneth Casson Leighton
2017-11-20 16:43:15 UTC
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Post by Luke Kenneth Casson Leighton
suggestions on how
to contact them appreciated.
thx ron. i got in touch with them, have been talking for a day, set
this up in order to keep track:
http://rhombus-tech.net/riscv/shakti/m_class/ - nothing official.

l.

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zap
2017-11-20 23:12:35 UTC
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Post by Luke Kenneth Casson Leighton
thx ron. i got in touch with them, have been talking for a day, set
http://rhombus-tech.net/riscv/shakti/m_class/ - nothing official.
l.
I am surprised I thought you would want the c class?

Do you think the m class will be lightweight enough for your purposes?
Post by Luke Kenneth Casson Leighton
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Luke Kenneth Casson Leighton
2017-11-21 03:38:31 UTC
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Post by zap
I am surprised I thought you would want the c class?
that's industrial.
Post by zap
Do you think the m class will be lightweight enough for your purposes?
it's the "mobile" class. get this: in 28nm they're looking at 600mW
power consumption for the m-class :)

l.

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Bill Kontos
2017-11-21 09:47:38 UTC
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On Tue, Nov 21, 2017 at 5:38 AM, Luke Kenneth Casson Leighton
Post by Luke Kenneth Casson Leighton
it's the "mobile" class. get this: in 28nm they're looking at 600mW
power consumption for the m-class :)
600mW sound like an aweful little for desktop use. I can't fathom
javascript loading speeds in such a package. For reference my phone
has a 3 watt chip( lg g3, snapdragon 801, 28nm) and I do notice some
lag with webpages. Now granted the high rez screen (1440 x 2560)
doesn't help but 600mW vs 3 W looks like a big drop.

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Luke Kenneth Casson Leighton
2017-11-21 09:58:08 UTC
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---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
Post by Bill Kontos
600mW sound like an aweful little for desktop use. I can't fathom
javascript loading speeds in such a package. For reference my phone
has a 3 watt chip( lg g3, snapdragon 801, 28nm) and I do notice some
lag with webpages. Now granted the high rez screen (1440 x 2560)
doesn't help but 600mW vs 3 W looks like a big drop.
RISC-V is *significantly* less power-hungry, performance/watt. also,
those 3 watts will include a Monster GPU, which will be being used for
accelerated graphics. and, there will be *two* 32-bit data-wide DDR3
interfaces, not the one. that'll be 600mW minus the interfaces btw
(including DDR3 driving and GPIO).

l.

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Bill Kontos
2017-11-21 10:15:47 UTC
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On Tue, Nov 21, 2017 at 11:58 AM, Luke Kenneth Casson Leighton
Post by Luke Kenneth Casson Leighton
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
RISC-V is *significantly* less power-hungry, performance/watt. also,
those 3 watts will include a Monster GPU, which will be being used for
accelerated graphics. and, there will be *two* 32-bit data-wide DDR3
interfaces, not the one. that'll be 600mW minus the interfaces btw
(including DDR3 driving and GPIO).
The A72 which they quote as their target is consuming 700-900 watts
per core, let alone the entire package. If they can drop power
consumption that much( assuming a quad core ~75% less power
consumption) then this is way more revolutionary than I thought.

Does that cover all the specialized hardware and video accel too?.
What's your definition of a monster gpu? Running 1080p at 60hz on a
browser is a must imo and wether we like it or not wayland is the
future so it will also need some sort of opengl compliant gpu just for
futureproofing.

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Luke Kenneth Casson Leighton
2017-11-21 10:23:20 UTC
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Post by Bill Kontos
The A72 which they quote as their target is consuming 700-900 watts
per core, let alone the entire package. If they can drop power
consumption that much( assuming a quad core ~75% less power
consumption) then this is way more revolutionary than I thought.
there's a paper comparing the two in 45nm, and yes RISC-V was around
half the power.
Post by Bill Kontos
Does that cover all the specialized hardware and video accel too?.
no.
Post by Bill Kontos
What's your definition of a monster gpu?
MALI T650 or so (whatever it is). not MALI-400, that's "little monster" :)
Post by Bill Kontos
Running 1080p at 60hz on a
browser is a must imo and wether we like it or not wayland is the
future so it will also need some sort of opengl compliant gpu just for
futureproofing.
the initial plan is to use the main processor with some basic SIMD
vector-processing instructions, which in quad-core would be more than
adequate.

bear in mind this is - preliminarily - to be around a USD $3 SoC with
between 320 and 400 pins.

l.

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Bill Kontos
2017-11-21 11:44:26 UTC
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On Tue, Nov 21, 2017 at 12:23 PM, Luke Kenneth Casson Leighton
Post by Luke Kenneth Casson Leighton
the initial plan is to use the main processor with some basic SIMD
vector-processing instructions, which in quad-core would be more than
adequate.
bear in mind this is - preliminarily - to be around a USD $3 SoC with
between 320 and 400 pins.
Alright that makes sense. Thanks for your time explaining it to me.

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Luke Kenneth Casson Leighton
2017-11-21 13:08:04 UTC
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---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
Post by Bill Kontos
On Tue, Nov 21, 2017 at 12:23 PM, Luke Kenneth Casson Leighton
Post by Luke Kenneth Casson Leighton
the initial plan is to use the main processor with some basic SIMD
vector-processing instructions, which in quad-core would be more than
adequate.
bear in mind this is - preliminarily - to be around a USD $3 SoC with
between 320 and 400 pins.
Alright that makes sense. Thanks for your time explaining it to me.
wheww, no deliberate mistakes spotted... :)

http://rhombus-tech.net/riscv/shakti/m_class/
http://rhombus-tech.net/riscv/shakti/m_class/pinouts/
http://rhombus-tech.net/riscv/shakti/m_class/pinouts.py

l.

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Luke Kenneth Casson Leighton
2017-11-21 21:23:19 UTC
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https://pdfs.semanticscholar.org/f6d5/e754da444b7ede6e4eeaf0d61e8cbb82ade9.pdf

https://arxiv.org/abs/1607.02318

so, the compression and something called macro-op fusion results in a
significant reduction in code size that happens also to result in less
cache usage and also faster execution time. how about that, huh? :)

l.

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Bill Kontos
2017-11-22 00:09:12 UTC
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On Tue, Nov 21, 2017 at 11:23 PM, Luke Kenneth Casson Leighton
Post by Luke Kenneth Casson Leighton
https://pdfs.semanticscholar.org/f6d5/e754da444b7ede6e4eeaf0d61e8cbb82ade9.pdf
https://arxiv.org/abs/1607.02318
so, the compression and something called macro-op fusion results in a
significant reduction in code size that happens also to result in less
cache usage and also faster execution time. how about that, huh? :)
Yes that was the entire point of risc-v, to make a risc isa with what
we learned from the mistakes of the past( there is a video going in
depth on the risc-v youtube channel about instruction density that I
can't seem to locate right now, but anyway removing the extra step
x86-64 has makes perfect sense). Although from your second link the
snapdragon 801 example that I gave before is supposed to be slightly
denser or equal to the compressed version of risc v, so this alone
doesn't seem to explain the difference. Anyway, if those are their
targets we'll have to wait and see what they come up with.

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Luke Kenneth Casson Leighton
2017-11-22 02:32:32 UTC
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could i ask people for some help, here?

http://rhombus-tech.net/riscv/shakti/m_class/pinouts/
http://rhombus-tech.net/riscv/shakti/m_class/pinouts.py

i'm looking for scenarios, to be added to the above, as "tests" of the
SoC multiplexing pinouts. it's a mobile-class, 32-bit-wire
DDR3/DDR3L/LPDDR3 RAM, 64-bit, 28nm, so probably... 2ghz or so,
quad-core, and has the interfaces listed on
http://rhombus-tech.net/riscv/shakti/m_class/

i'm just about to cover the smartphone/tablet scenario, can anyone
think of any other scenarios? would anyone like to submit a patch to
the python code which includes the laptop scenario? or any other one?

tia,

l.

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Luke Kenneth Casson Leighton
2017-11-22 05:13:07 UTC
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http://rhombus-tech.net/riscv/shakti/m_class/pinouts/

added the smartphone/tablet scenario, added DDR3, SYS and POWER
pins.... total comes to 290! that's around 18x18 on a side, maybe
19x19 to make space for routing, which in a BGA form-factor @ 0.8mm
pitch would be a 15x15mm package!

0.8mm deliberately because it's far, far easier to do a PCB with
larger vias, and you can (i think) just about get a 4mil maybe even a
5mil trace in between 0.8mm BGA pads.

cooool :)

l.

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Luke Kenneth Casson Leighton
2017-12-01 15:38:31 UTC
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http://rhombus-tech.net/riscv/shakti/m_class/ramanalysis/

also added a section analysing options for DRAM. unsurprisingly the
top contender is DDR3/DDR3L/LPDDR3. in 3-8 years time it might be
DDR4/LPDDR4 but the *massive* speed (1200mhz) is completely insane to
contemplate right now. and availability is.... yyeahhh....

l.

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