On Sun, Jul 17, 2016 at 11:02 PM, Manuel A. Fernandez Montecelo
Post by Manuel A. Fernandez MonteceloHi all,
Post by Paul BoddiePost by Luke Kenneth Casson Leightonthe page is now live, and runs till the 26th august. please do help
push that out to as many people as you can, blog about it, etc. we
have thinkpenguin writing about it, liliputing is doing an article,
i'll create a slashdot article, i'll be in touch with wired later
today and so on.
https://www.crowdsupply.com/eoma68/micro-desktop
Congratulations on getting this far!
+1! Congrats, Luke!
thanks manuel. we're at 54% of the total MOQ numbers needed for the
Computer Card production run, which is great.
Post by Manuel A. Fernandez MonteceloMIPS it's a more realistic possibility, but I am not sure if IC1T is a
very good option, if it has no foothold in the market yet, has zero
distributions supporting it, and it doesn't offer clear advantages in
other areas (??). I wouldn't mind at all to get one of those, but I am
not sure if many people will follow... so would be bad in terms of
effectiveness.
if it can't have debian... yeah. as in, because the open64.net
compiler "isn't called gcc", it's almost impossible to *do* a debian
port.
Post by Manuel A. Fernandez MonteceloIf it's for something more experimental like perhaps the IC1T would be,
I'd consider the possibility of exploring RISC-V [1] based designs like
the recently launched SiFive ones [2].
The development is more in-line with FOSS (even if some aspects are not
100% perfect), hopefully there will be no need for blobs or NDAs or
problems for booting. And with 64-bits, it is well prepared to be
usable for several decades to come [3].
ok, what goes into a successful SoC? let's go through ths list:
* Video output: HDMI, LCD (RGB/TTL/LVDS/MIPI/eDP), maybe TV (Composite)
* Memory: DDR2 through to DDR4 and not forgetting LPDDR2/3 *and* DDR3L...
* Storage (SATA, SD/MMC, eMMC, NAND)
* Network (Ethernet)
* USB (1.0 through 3.1) multiple thereof including USB-OTG
* GPIO (plain GPIO) and also EINT-capable GPIO
* Audio (I2S AC97 as well as Analog - Headphones, Mic etc.)
* PCIe
* General-purpose sensors/peripherals (I2C, UART, SPI up to 4 lane)
then also for a successful mass-market SoC you also need:
* 3D Graphics GPU
* 2D Graphics GPU
* Video Decode / Encode
* Crypto Co-processor (which saves power)
and finally - last *AND LEAST*:
* A general-purpose processor.
yes really, with all that huge amount of extra stuff above, the
processor *really is* last and least! :) it's also, in the RISC
world, one of the smallest sections of the SoC, taking up something
like ONE PERCENT in the corner. 1st level cache takes up a whopping
15-20%. The "Memory Bus" down the middle of the processor is a
whopping 15% the width of the entire die, with branches off left and
right to different peripherals (including the processor).
now for licensing costs of all those hard macros, it works out
something like: $350,000 for DDR memory bus (32-bit-wide data), $50k
for SATA, $50k for each USB3, $50k for GPIO/Audio/I2C/UART etc, $50k
for Ethernet.... pretty soon you are at $USD 3 million for licensing
of all the hard macros needed to make a successful SoC.
... but if you *don't do* that licensing, and instead try to replicate
them all, you are immediately placing the entire project at risk.
bear in mind that TSMC won't talk to you if you make a failed chip
(first time) because you're wasting their time. and it costs $USD 2
*MILLION* for the production masks (the lithographic masks like an OHP
plastic sheet)
... so against that background can you see that to focus on the
*actual* processor's *instruction set* - to make a totally new
architecture - is pretty much irrelevant as far as making an *actual
processor* is concerned?
and then once that's done you *still* need to port OSes to it!
my feeling is, we would be much better off talking to Loongson and
seeing if they'd be up for a licensing deal of their MIPS64
architecture. apart from anything the Loongson 3G and above have
emulation in hardware of the top 200 x86 instructions which makes it
possible for them to accelerate non-native QEMU up to 70% of the
native MIPS64 processor's clock rate. which is pretty awesome.
l.
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