[Arm-netbook] Rv: Update: 2.7.4 EOMA68-A20 Cards Arrived

[el_gallo_azul via arm-netbook]

I'd be happy enough to supply my own MicroSD card (in place of the TSSOP-48 NAND IC).
 
Greg Flint
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[Luke Kenneth Casson Leighton]

On Wed, Jun 21, 2017 at 5:31 AM, el_gallo_azul via arm-netbook

I'd be happy enough to supply my own MicroSD card (in place of the TSSOP-48 NAND IC).

thanks greg. very much appreciated.

Greg Flint
#yiv0042324540 body, #yiv0042324540 #yiv0042324540bodyTable,

yarg, greg, eek! please do read up on how to interact with other
people on mailing lists! you received a welcome message, with links
on posting style and posting netiquette. please read it!

l.

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Post by Luke Kenneth Casson Leighton
On Wed, Jun 21, 2017 at 5:31 AM, el_gallo_azul via arm-netbook

I'd be happy enough to supply my own MicroSD card (in place of the TSSOP-48 NAND IC).

thanks greg. very much appreciated.

Greg Flint
#yiv0042324540 body, #yiv0042324540 #yiv0042324540bodyTable,

yarg, greg, eek! please do read up on how to interact with other
people on mailing lists! you received a welcome message, with links
on posting style and posting netiquette. please read it!

You sure that this is not the result of the auto HTML converter?

Post by Luke Kenneth Casson Leighton
l.
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Post by m***@gmail.com

Post by Luke Kenneth Casson Leighton

Post by el_gallo_azul via arm-netbook
Greg Flint
#yiv0042324540 body, #yiv0042324540 #yiv0042324540bodyTable,

yarg, greg, eek! please do read up on how to interact with other
people on mailing lists! you received a welcome message, with links
on posting style and posting netiquette. please read it!

You sure that this is not the result of the auto HTML converter?

not sure. greg forwarded a copy of the (entire) update as a first
attempt: it was rejected due to size. we'll find out what he did when
he responds but i believe he may have tried manually editing the
message.

l.

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[zap]

I wish you the best Luke. I will also say, that if you cannot get hdmi
working it won't bother me. Also, if micro sd cards are too expensive,
I really don't care about that either. It's all good dude.

Just as long as the computer is as functional as you can make it.

:)

I really appreciate what the free software community does for our world.
If not for GNU and free software supporters like you, I would really
extremely frightened of our current world... government intimidation and
what not...

My bad if this comes across as sappy, meh...

One question though, how is reverse engineering the rockchip going?

Just curious.


Anyways, peace to ya Luke and I wish you well.




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[Luke Kenneth Casson Leighton]

Post by zap
I wish you the best Luke. I will also say, that if you cannot get hdmi
working it won't bother me. Also, if micro sd cards are too expensive,
I really don't care about that either. It's all good dude.
Just as long as the computer is as functional as you can make it.

appreciated. there are however some people who would have pledged
only for the card, and the cable kit: they'll be expecting to use the
cards stand-alone.

argh.

Post by zap
:)
I really appreciate what the free software community does for our world.
If not for GNU and free software supporters like you, I would really
extremely frightened of our current world... government intimidation and
what not...

thx zap

Post by zap
My bad if this comes across as sappy, meh...

pffh :)

Post by zap
One question though, how is reverse engineering the rockchip going?

i stopped working on it for a while as i may have a lead on a better
SoC, the RK3388 (yes it really does exist). also i'm waiting for some
equipmnt to arrive so i can put on 2 extra DDR3x16 RAM ICs.

l.

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[Vincent Legoll]

On Wed, Jun 21, 2017 at 5:20 PM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
appreciated. there are however some people who would have pledged
only for the card, and the cable kit: they'll be expecting to use the
cards stand-alone.

Yes, there are some of those, I'm one for instance.

I would personally be less bothered by the lack of an SD card than the
missing HDMI.

[Pablo Rath]

Post by Vincent Legoll
On Wed, Jun 21, 2017 at 5:20 PM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
appreciated. there are however some people who would have pledged
only for the card, and the cable kit: they'll be expecting to use the
cards stand-alone.

Yes, there are some of those, I'm one for instance.

Me too.

Post by Vincent Legoll
I would personally be less bothered by the lack of an SD card than the
missing HDMI.

To provide my own SD card doesn't bother me at all.
The missing HDMI would be bad. If this scenario happens maybe we can
talk about a special offer for a micro desktop.

kind regards
Pablo

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Post by Pablo Rath
To provide my own SD card doesn't bother me at all.
The missing HDMI would be bad.

i know.

Post by Pablo Rath
If this scenario happens maybe we can
talk about a special offer for a micro desktop.

that's a great idea.

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[zap]

Post by Luke Kenneth Casson Leighton

Post by Pablo Rath
To provide my own SD card doesn't bother me at all.
The missing HDMI would be bad.

i know.

Honestly, I am beginning to wonder... because don't you need some memory
storage on the system to boot it up?

I think some people on request may want it already ready to go with a
hop and a skip.

but more importantly documentation with the order on how to start things
up, etc,

Post by Luke Kenneth Casson Leighton

Post by Pablo Rath
If this scenario happens maybe we can
talk about a special offer for a micro desktop.

that's a great idea.
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[Luke Kenneth Casson Leighton]

Post by zap
Honestly, I am beginning to wonder... because don't you need some memory
storage on the system to boot it up?

one of the available boot options (SDC0, NAND, SDC2, SPI) yes.

Post by zap
I think some people on request may want it already ready to go with a
hop and a skip.

indeed.

Post by zap
but more importantly documentation with the order on how to start things
up, etc,

that bit's done-ish but it'll be necessary to duplicate it on an
appropriate location for the project.

the issue we have is that the available budget is now severely and
unavoidably depleted (as already outlined multiple times). buying
1,000 8GB MicroSD cards is no longer really an option.

l.

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[zap]

Post by Luke Kenneth Casson Leighton

Post by zap
but more importantly documentation with the order on how to start things
up, etc,

that bit's done-ish but it'll be necessary to duplicate it on an
appropriate location for the project.
the issue we have is that the available budget is now severely and
unavoidably depleted (as already outlined multiple times). buying
1,000 8GB MicroSD cards is no longer really an option.

Well, even on request if we are willing to pay for the sd cards? just
curious.


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[Luke Kenneth Casson Leighton]

Post by zap

Post by Luke Kenneth Casson Leighton
1,000 8GB MicroSD cards is no longer really an option.

Well, even on request if we are willing to pay for the sd cards? just
curious.

that would work.

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[zap]

Post by Luke Kenneth Casson Leighton

Post by zap

Post by Luke Kenneth Casson Leighton
1,000 8GB MicroSD cards is no longer really an option.

Well, even on request if we are willing to pay for the sd cards? just
curious.

that would work.

Ah, okay good to know.

Post by Luke Kenneth Casson Leighton
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[zap]

Post by Luke Kenneth Casson Leighton

Post by zap
I wish you the best Luke. I will also say, that if you cannot get hdmi
working it won't bother me. Also, if micro sd cards are too expensive,
I really don't care about that either. It's all good dude.
Just as long as the computer is as functional as you can make it.

appreciated. there are however some people who would have pledged
only for the card, and the cable kit: they'll be expecting to use the
cards stand-alone.
argh.

I am hopeful that you will figure that out

Post by Luke Kenneth Casson Leighton

Post by zap
One question though, how is reverse engineering the rockchip going?

i stopped working on it for a while as i may have a lead on a better
SoC, the RK3388 (yes it really does exist). also i'm waiting for some
equipmnt to arrive so i can put on 2 extra DDR3x16 RAM ICs.

Wait... how much ram would you have then as supported. I mean, you did
say 4gb would be the limit right? Also, the RK3388 will it be easier or
harder to reverse engineer? just curious.

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[zap]

Post by zap

Post by Luke Kenneth Casson Leighton
i stopped working on it for a while as i may have a lead on a better
SoC, the RK3388 (yes it really does exist). also i'm waiting for some
equipmnt to arrive so i can put on 2 extra DDR3x16 RAM ICs.

Wait... how much ram would you have then as supported. I mean, you did
say 4gb would be the limit right? Also, the RK3388 will it be easier or
harder to reverse engineer? just curious.

Let me know if this is a problem that I ask this, but where do I find
rk3388 on the web, I was curious about its description and what not,

Is this processor a octacore? just curious because if so, it might be
called rk3368 and not rk3388.

Again though, I still wonder about its capabilities.

Post by zap
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[Luke Kenneth Casson Leighton]

Post by zap
Let me know if this is a problem that I ask this, but where do I find
rk3388 on the web, I was curious about its description and what not,

you don't.

Post by zap
Is this processor a octacore?

quad.

Post by zap
just curious because if so, it might be
called rk3368 and not rk3388.

it's not.

Post by zap
Again though, I still wonder about its capabilities.

64-bit cut-down version of rk3288 targetted at media centres.

l.

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[zap]

Post by Luke Kenneth Casson Leighton

Post by zap
Let me know if this is a problem that I ask this, but where do I find
rk3388 on the web, I was curious about its description and what not,

you don't.

Post by zap
Is this processor a octacore?

quad.

Post by zap
just curious because if so, it might be
called rk3368 and not rk3388.

it's not.

Post by zap
Again though, I still wonder about its capabilities.

64-bit cut-down version of rk3288 targetted at media centres.

Okay, thanks for telling me, Luke. Appreciate it. I was confused heh.



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[Luke Kenneth Casson Leighton]

Post by zap
Wait... how much ram would you have then as supported. I mean, you did
say 4gb would be the limit right?

4gb yes.

Post by zap
Also, the RK3388 will it be easier or
harder to reverse engineer? just curious.

contact is working on nda-free full info including pcb design.

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[Richard Wilbur]

While i would appreciate having hdmi. I’ll be understanding if that
doesn’t happen in the end. Anyway, there be the new/next EOMA68 computer
cards to look forward too anyway :)

In the interest of solving the challenge of integrating the HDMI connector, I have a few questions:
1. Is there a publicly-accessible spot from which I can download the schematics and pcb files? (I found http://rhombus-tech.net/allwinner_a10/pcb/ is that the correct place?)
2. How many copper layers does this board have?
3. What is the minimum trace size?
4. What is the minimum trace spacing?
5. Is the minimum plated through hole diameter 6 mil?
6. Did this message (composed on my iPhone E-mail client) come through in HTML or simple text?

The Amphenol part has 0.15mm clearance between lands for even row of pins and board edge in cutout while Molex 468753011 has 0.9mm clearance in the same spot.

Sincerely,
Richard
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[Hendrik Boom]

On Mon, Jun 26, 2017 at 09:56:12PM -0600, Richard Wilbur wrote:
...
...

Post by Richard Wilbur
6. Did this message (composed on my iPhone E-mail client) come through in HTML or simple text?

I got it as simple text. There was not even an HTML attachment.

-- hendrik

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[Richard Wilbur]

Post by Hendrik Boom

Post by Richard Wilbur
6. Did this message (composed on my iPhone E-mail client) come through in HTML or simple text?

I got it as simple text. There was not even an HTML attachment.

Thanks for the feedback. I'm so thankful it is text as that greatly simplifies my interaction with this mailing list when I am away from my desktop!
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On Tue, Jun 27, 2017 at 4:56 AM, Richard Wilbur

Post by Richard Wilbur

While i would appreciate having hdmi. I’ll be understanding if that
doesn’t happen in the end. Anyway, there be the new/next EOMA68 computer
cards to look forward too anyway :)

1. Is there a publicly-accessible spot from which I can download the schematics and pcb files? (I found http://rhombus-tech.net/allwinner_a10/pcb/ is that the correct place?)

not yet.

Post by Richard Wilbur
2. How many copper layers does this board have?

6

Post by Richard Wilbur
3. What is the minimum trace size?

3.5 mil

Post by Richard Wilbur
4. What is the minimum trace spacing?

3.5 mil

Post by Richard Wilbur
5. Is the minimum plated through hole diameter 6 mil?

yes

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[Richard Wilbur]

Until I get an opportunity to review the design files it is difficult to make detailed recommendations. Have you identified which signals are affected? Have you been able to determine which signals are leaking into the affected signals?

If the image posted with the update[*] is representative of the board geometry, it looks like there could be direct electromagnetic coupling of the 4 HDMI differential pair transmission lines as follows: HTX0 <-> HTX1, HTX2 <-> HTX1, HTX2 <-> HTXC.
This could be caused by (and ameliorated by) the following:
1. HTX0 <-> HTX1
Cause: Microstrips are antennae with cross-section consisting of the area between the pair of differential conductors. These two are traveling in parallel on different layers through the ESD section with overlapping antenna area.
Possible Remediation: move U10 "up" or "down" far enough relative to the pair on the other side of the pcb that these two pairs don't exhibit any overlapping antenna area
2. HTX2 <-> HTX1
Cause: HTX1P has length correction loop just before reaching the land on CON3 pin 6. I applaud the strategy of clustering impedance discontinuities, thus putting the loop near CON3. The problem is that this expanded antenna cross-section on HTX1 face an HTX2 microstrip antenna.
Possible Remediation: Move HTX1P length-compensating loop so it doesn't couple to any other high-speed antenna.
3. HTX2 <-> HTXC
Cause: Near edge of vignette, microstrip antennae directly facing each other as they leave the field of view.
Possible Remediation: Move microstrips relative to each other so that there is no shared cross section.

[Luke Kenneth Casson Leighton]

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On Fri, Jun 30, 2017 at 3:32 AM, Richard Wilbur

Post by Richard Wilbur
Until I get an opportunity to review the design files it is difficult to make detailed recommendations. Have you identified which signals are affected?

no - i do not have access to equipment which will allow me to make
such a determination.

Post by Richard Wilbur
Have you been able to determine which signals are leaking into the affected signals?

ditto... basically this is all guess-work and experimentation.

ok, so what i'm planning to do, richard, is a redesign of this entire
area, starting by widening the PCB by 1mm. this should allow me to
put several diff-pairs on the same layer (i'll start by trying to put
them all on layer 3, see how that goes).

would you be happy to advise before it goes to pre-production?

l.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Fri, Jun 30, 2017 at 3:32 AM, Richard Wilbur

Post by Richard Wilbur
Until I get an opportunity to review the design files it is difficult to make detailed recommendations. Have you identified which signals are affected?

no - i do not have access to equipment which will allow me to make
such a determination.

I guess you would need a pretty fast oscilloscope with at least 1 GHz bandwidth

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Have you been able to determine which signals are leaking into the affected signals?

ditto... basically this is all guess-work and experimentation.
ok, so what i'm planning to do, richard, is a redesign of this entire
area, starting by widening the PCB by 1mm. this should allow me to
put several diff-pairs on the same layer (i'll start by trying to put
them all on layer 3, see how that goes).
would you be happy to advise before it goes to pre-production?
l.
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[Richard Wilbur]

Sent from my iPhone

Post by Luke Kenneth Casson Leighton
On Fri, Jun 30, 2017 at 3:32 AM, Richard Wilbur

Post by Richard Wilbur
Have you identified which signals are affected?

no - i do not have access to equipment which will allow me to make
such a determination.

I'll check to see whether I can get some lab time up at the university (where I took the lion's share of my electrical engineering coursework).

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Have you been able to determine which signals are leaking into the affected signals?

ditto... basically this is all guess-work and experimentation.

Well congratulations on many good guesses and what sounds like a relatively successful experiment!

The fact that I don't know the layer stack for the board throws in some more uncertainty. I don't know whether those differential pairs were spending a lot of time over a ground plane. When the differential pairs crossed paths did they do so over separate ground planes, et cetera?

Post by Luke Kenneth Casson Leighton
ok, so what i'm planning to do, richard, is a redesign of this entire
area, starting by widening the PCB by 1mm.

Does that still meet your design goal for EOMA68 form factor? I wouldn't sacrifice an important design goal, yet. I wouldn't be surprised if we can pack a working layout into your original outline. On the other hand, more space can make the layout easier.

Post by Luke Kenneth Casson Leighton
this should allow me to put several diff-pairs on the same layer
(i'll start by trying to put them all on layer 3, see how that goes).

You said the board has 6 layers. Does that mean layer 3 is in the midst of the stack or on the outside? If it's inside, you could use striplines for the differential pairs. It'll require three layers (two of them ground) but it is about as close to a TEM waveguide as you can get in a PCB.

Post by Luke Kenneth Casson Leighton
would you be happy to advise before it goes to pre-production?

I would be overjoyed to put this somewhat arcane knowledge to some good use. In other words, "Yes!"

Reading an application note on HDMI from Texas Instruments[*] I noticed they mentioned a clock rate of 340 MHz and


Reference:
[*] _HDMI Design Guide_, http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-138-01-00-00-10-65-80/Texas-Instruments-HDMI-Design-Guide.pdf
[2] SLLA324 February 2012 Application Report, "TPD12S016 PCB Layout Guidelines for HDMI ESD"



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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Fri, Jun 30, 2017 at 3:32 AM, Richard Wilbur

Post by Richard Wilbur
Have you identified which signals are affected?

no - i do not have access to equipment which will allow me to make
such a determination.

I'll check to see whether I can get some lab time up at the university (where I took the lion's share of my electrical engineering coursework).

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Have you been able to determine which signals are leaking into the affected signals?

ditto... basically this is all guess-work and experimentation.

Well congratulations on many good guesses and what sounds like a relatively successful experiment!

The fact that I don't know the layer stack for the board throws in some more uncertainty. I don't know whether those differential pairs were spending a lot of time over a ground plane. When the differential pairs crossed paths did they do so over separate ground planes, et cetera?

Post by Luke Kenneth Casson Leighton
ok, so what i'm planning to do, richard, is a redesign of this entire
area, starting by widening the PCB by 1mm.

Does that still meet your design goal for EOMA68 form factor? I wouldn't sacrifice an important design goal, yet. I wouldn't be surprised if we can pack a working layout into your original outline. On the other hand, more space can make the layout easier.

Post by Luke Kenneth Casson Leighton
this should allow me to put several diff-pairs on the same layer
(i'll start by trying to put them all on layer 3, see how that goes).

You said the board has 6 layers. Does that mean layer 3 is in the midst of the stack or on the outside? If it's inside, you could use striplines for the differential pairs[1]. It'll require three layers (two of them ground) but it is about as close to a TEM waveguide as you can get in a PCB.

Post by Luke Kenneth Casson Leighton
would you be happy to advise before it goes to pre-production?

I would be overjoyed to put this somewhat arcane knowledge to some good use. In other words, "Yes!"

Reading an application note on HDMI from Texas Instruments[2] I noticed they mentioned a clock rate of 340 MHz and with a data rate of 3.4 Gb/s. In the interest of characterizing the problem at hand I would like to find a reference that describes the signals of this standard (HDMI v1.4).

Sorry for the noise. My last two posts were prematurely sent when I was trying to type (on my phone keyboard) and accidentally hit a/an conveniently/inconveniently placed "Send" button. I am trying to make peace with this user interface.

My wife gave me a tip: remove the "To:" address until you are ready to send the message as without a destination address the "Send" button is disabled.
--
Richard

References:
[1] _HDMI Design Guide_, http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-138-01-00-00-10-65-80/Texas-Instruments-HDMI-Design-Guide.pdf
[2] SLLA324 February 2012 Application Report, "TPD12S016 PCB Layout Guidelines for HDMI ESD"

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[Luke Kenneth Casson Leighton]

Post by Richard Wilbur
Sent from my iPhone

Post by Luke Kenneth Casson Leighton
On Fri, Jun 30, 2017 at 3:32 AM, Richard Wilbur

Post by Richard Wilbur
Have you identified which signals are affected?

no - i do not have access to equipment which will allow me to make
such a determination.

I'll check to see whether I can get some lab time up at the university (where I took the lion's share of my electrical engineering coursework).

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
Have you been able to determine which signals are leaking into the affected signals?

ditto... basically this is all guess-work and experimentation.

Well congratulations on many good guesses and what sounds like a relatively successful experiment!
The fact that I don't know the layer stack for the board

6 layer FR4 1.2mm, top gnd sig, pwr, gnd, bot.

Post by Richard Wilbur
throws in some more uncertainty. I don't know whether those differential pairs were spending a lot of time over a ground plane. When the differential pairs crossed paths did they do so over separate ground planes, et cetera?

i'm now restricting the dff pairs to top and bottom. the majority of
time is bottom. space at the edge is now sufficient to do that.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
ok, so what i'm planning to do, richard, is a redesign of this entire
area, starting by widening the PCB by 1mm.

Does that still meet your design goal for EOMA68 form factor?

yes. actually without the expansion the plastic surround flops about
and the casework can drop off. with the extra size the plastic edges
stay in place and the catches along the metal case then also stay in
place.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
this should allow me to put several diff-pairs on the same layer
(i'll start by trying to put them all on layer 3, see how that goes).

You said the board has 6 layers. Does that mean layer 3 is in the midst of the stack or on the outside?

yes but next to the power plane, where i have run 5V power and 3.3v
(and can't move them).

Post by Richard Wilbur
If it's inside, you could use striplines for the differential pairs. It'll require three layers (two of them ground) but it is about as close to a TEM waveguide as you can get in a PCB.

Post by Luke Kenneth Casson Leighton
would you be happy to advise before it goes to pre-production?

I would be overjoyed to put this somewhat arcane knowledge to some good use. In other words, "Yes!"

yay!

Post by Richard Wilbur
Reading an application note on HDMI from Texas Instruments[*] I noticed they mentioned a clock rate of 340 MHz and

340mhz is not as bad as i was expecting.

l.

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[Luke Kenneth Casson Leighton]

ok richard i've redone the layout, and published 3 images here:
http://rhombus-tech.net/allwinner_a10/news/

the 3rd one - showing the full extent of the 4 diff pairs - is
enormous (right-mouse-button, view image) as it's a screenshot from
this laptop's 3000x1800 LCD. so you should be able to zoom in without
losing resolution.

unfortunately since taking the screenshot i noticed that the GND
runners between the diff-pairs have been removed: i will restore
these. PADS has a bug where when you switch off "locking" of tracks /
nets it can suddenly decide "ohhh i'll just re-analyse this lot and
remove anything i don't like the look of" which in this case involved
removing several shielding GND vias and some of the manual GND tracks
that help with shielding, in places where flood-fill could not reach
due to the small size.

anyway i'll add back in the 5mil tracks between the diff-pairs, if
you're wondering why they're missing (they're not).

to make it easier to view i switched off layers 2-4, leaving top and
bottom only. the HDMI tracks are only *on* top and bottom, anyway.
they're all length-matched diff-pairs to within 0.1mm, the clock lines
are something like 52.8 mm and i think the shortest one, Tx2, is
48.5mm something like that.

l.

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[Richard Wilbur]

Post by Richard Wilbur
http://rhombus-tech.net/allwinner_a10/news/

Thanks for letting me know. I took an initial peek at the images and they look like you addressed the points I mentioned.

I'm going to be a day or two getting back with more detailed questions as today is a holiday here and we have family visiting till Thursday.

A couple questions that spring immediately to mind:
1. How continuous are the ground planes under the differential pairs? (Are there voids in the ground planes under the differential pairs?)
2. The intra-pair length sounds well-matched, my understanding of the inter-pair skew is that the requirement is in terms of the clock speed Δt <= 0.2 Tcharacter. For 225 MHz clock the application note spoke of 888ps. So we'll be interested in determining the maximum clock rate and speed of propagation.

I'll also have some questions about dimensions and geometry.

Thank you for the opportunity to participate.

[Luke Kenneth Casson Leighton]

Post by Richard Wilbur

Post by Richard Wilbur
http://rhombus-tech.net/allwinner_a10/news/

Thanks for letting me know. I took an initial peek at the images and they look like you addressed the points I mentioned.

yay

Post by Richard Wilbur
I'm going to be a day or two getting back with more detailed questions as today is a holiday here and we have family visiting till Thursday.

nice

Post by Richard Wilbur
1. How continuous are the ground planes under the differential pairs? (Are there voids in the ground planes under the differential pairs?)

no. layers 2 and 5 are solid ground planes. vias obviously go
through those , full vias only. non-GND vias also obviously create
small interruptions but that's all

Post by Richard Wilbur
2. The intra-pair length sounds well-matched, my understanding of the inter-pair skew is that the requirement is in terms of the clock speed Δt <= 0.2 Tcharacter. For 225 MHz clock the application note spoke of 888ps. So we'll be interested in determining the maximum clock rate and speed of propagation.

3e8 m/sec * 888e-12 = 0.2664 metres.... which is 266.4 mm... way
beyond anything which would indicate some kind of problem if the board
is 78mm long and the skew is only 2mm.

Post by Richard Wilbur
I'll also have some questions about dimensions and geometry.

ack.

Post by Richard Wilbur
Thank you for the opportunity to participate.

always appreciate the help.

l.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
[…]

Post by Richard Wilbur
1. How continuous are the ground planes under the differential pairs? (Are there voids in the ground planes under the differential pairs?)

no. layers 2 and 5 are solid ground planes. vias obviously go
through those , full vias only. non-GND vias also obviously create
small interruptions but that's all

Wonderful! That's music to my ears. No major obstacles on return current path except the vias. So when we change signal layers, we'll need adjacent ground plane-to-ground plane vias to provide a nice low-impedance path for the return current in the ground planes.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
2. The intra-pair length sounds well-matched, my understanding of the inter-pair skew is that the requirement is in terms of the clock speed Δt <= 0.2 Tcharacter. For 225 MHz clock the application note spoke of 888ps. So we'll be interested in determining the maximum clock rate and speed of propagation.

3e8 m/sec * 888e-12 = 0.2664 metres.... which is 266.4 mm... way
beyond anything which would indicate some kind of problem if the board
is 78mm long and the skew is only 2mm.

You're on the right track and that is a good calculation for propagation in free space (vacuum). It turns out with relative permittivity of FR-4 fiberglass substrate our signal actually travels significantly slower which tightens our design parameters a little.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
I'll also have some questions about dimensions and geometry.

ack.

Not too awful. Just a few questions about how you are routing to control the impedance.
1. Are you using a 2-D field solver to determine the impedance and adjust design parameters accordingly(trace width, intra-pair spacing, inter-pair spacing, etc.)?
2. Are you working with your board fabricator to determine the design parameters mentioned above b
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[Richard Wilbur]

Sorry, that last post was far from complete and I'm working on a more complete set of questions and recommendations which I hope to get off to you tomorrow. Any answers will be appreciated, as usual.

I've been working on this primarily in the evenings over the last week or so and found 64 pages of "light, bed-time" reading.

We are back from a weekend without electricity, internet service, or cellular telephone service.

[Luke Kenneth Casson Leighton]

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On Mon, Jul 17, 2017 at 7:45 AM, Richard Wilbur

Post by Richard Wilbur
Sorry, that last post was far from complete and I'm working on a more complete set of questions and recommendations which I hope to get off to you tomorrow. Any answers will be appreciated, as usual.

i've done some improvements since, i'm just about to update them.

Post by Richard Wilbur
I've been working on this primarily in the evenings over the last week or so and found 64 pages of "light, bed-time" reading.
We are back from a weekend without electricity, internet service, or cellular telephone service.

niiiice :)

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On Mon, Jul 17, 2017 at 7:26 AM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
[…]

Post by Richard Wilbur
1. How continuous are the ground planes under the differential pairs? (Are there voids in the ground planes under the differential pairs?)

no. layers 2 and 5 are solid ground planes. vias obviously go
through those , full vias only. non-GND vias also obviously create
small interruptions but that's all

Wonderful! That's music to my ears. No major obstacles on return current path except the vias. So when we change signal layers, we'll need adjacent ground plane-to-ground plane vias to provide a nice low-impedance path for the return current in the ground planes.

i've added as many of these as i can fit. space is... very very tight.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
2. The intra-pair length sounds well-matched, my understanding of the inter-pair skew is that the requirement is in terms of the clock speed Δt <= 0.2 Tcharacter. For 225 MHz clock the application note spoke of 888ps. So we'll be interested in determining the maximum clock rate and speed of propagation.

3e8 m/sec * 888e-12 = 0.2664 metres.... which is 266.4 mm... way
beyond anything which would indicate some kind of problem if the board
is 78mm long and the skew is only 2mm.

You're on the right track and that is a good calculation for propagation in free space (vacuum). It turns out with relative permittivity of FR-4 fiberglass substrate our signal actually travels significantly slower which tightens our design parameters a little.

oh! duh! i forgot about that

Post by Richard Wilbur
Not too awful. Just a few questions about how you are routing to control the impedance.
1. Are you using a 2-D field solver to determine the impedance and adjust design parameters accordingly(trace width, intra-pair spacing, inter-pair spacing, etc.)?

PADS can calculate impedance based on board stack, track width and
track-to-track spacing... i'm... relying on that, and the fact that
the tracks are 50mm long.

Post by Richard Wilbur
2. Are you working with your board fabricator to determine the design parameters mentioned above b

nnaahh.

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[Richard Wilbur]

On Mon, Jul 17, 2017 at 1:16 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Mon, Jul 17, 2017 at 7:26 AM, Richard Wilbur

Post by Richard Wilbur
Wonderful! That's music to my ears. No major obstacles on return current path except the vias. So when we change signal layers, we'll need adjacent ground plane-to-ground plane vias to provide a nice low-impedance path for the return current in the ground planes.

i've added as many of these as i can fit. space is... very very tight.

For our differential pairs we should only need one return-current-path
via per signal via (and hopefully relatively adjacent to it) since we
are using ground planes for our reference planes. It is basically
trying to provide a relatively low-impedance path for the RF
(radio-frequency) return current in the reference planes (since when
we switch signal layers between top and bottom, our reference plane
changes).

Post by Luke Kenneth Casson Leighton
PADS can calculate impedance based on board stack, track width and
track-to-track spacing... i'm... relying on that, and the fact that
the tracks are 50mm long.

From what I'm reading this looks easiest (and best) to tackle in
segments of no more than 15mm at a time. Can PADS work with you on
one section of the path at a time? More details in next message.

1. Are you specifying the track width, track-to-track spacing, and
board stack or is PADS determining that for you?
2. What are you using for the ...
a. microstrip differential pair track widths,
b. intra-pair track spacing,
c. differential-pair-to-other track spacing?
3. What is your copper thickness on top and bottom layers?
4. What is the height of insulator between top layer and adjacent
ground reference layer?
5. What is the height of insulator between bottom layer and adjacent
ground reference layer?

--
Richard

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On Tue, Jul 18, 2017 at 6:16 PM, Richard Wilbur

Post by Richard Wilbur
On Mon, Jul 17, 2017 at 1:16 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Mon, Jul 17, 2017 at 7:26 AM, Richard Wilbur

Post by Richard Wilbur
Wonderful! That's music to my ears. No major obstacles on return current path except the vias. So when we change signal layers, we'll need adjacent ground plane-to-ground plane vias to provide a nice low-impedance path for the return current in the ground planes.

i've added as many of these as i can fit. space is... very very tight.

For our differential pairs we should only need one return-current-path
via per signal via (and hopefully relatively adjacent to it) since we
are using ground planes for our reference planes. It is basically
trying to provide a relatively low-impedance path for the RF
(radio-frequency) return current in the reference planes (since when
we switch signal layers between top and bottom, our reference plane
changes).

as best i can i've put the vias as close as possible. here's some new images

http://hands.com/~lkcl/eoma/a20_hdmi_review/

i've also lined the bottom edge with vias, and there are a lot along
the top of the diff-pairs, separating other signals.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
PADS can calculate impedance based on board stack, track width and
track-to-track spacing... i'm... relying on that, and the fact that
the tracks are 50mm long.

From what I'm reading this looks easiest (and best) to tackle in
segments of no more than 15mm at a time. Can PADS work with you on
one section of the path at a time?

mmm.. don't think so. i can select a pin pair and it tells me that
the impedance is 89 ohms.

Post by Richard Wilbur
More details in next message.
1. Are you specifying the track width,

minimum 5mil. specified in groups.

Post by Richard Wilbur
track-to-track spacing,

5mil minimum

Post by Richard Wilbur
and board stack

board thickness 47.3 (1.2mm), 1oz copper, 6.4mil on FR4.

Post by Richard Wilbur
or is PADS determining that for you?

how would it know?

Post by Richard Wilbur
2. What are you using for the ...
a. microstrip differential pair track widths,

5 mil

Post by Richard Wilbur
b. intra-pair track spacing,

5 mil

Post by Richard Wilbur
c. differential-pair-to-other track spacing?

5 mil

Post by Richard Wilbur
3. What is your copper thickness on top and bottom layers?

1oz

Post by Richard Wilbur
4. What is the height of insulator between top layer and adjacent
ground reference layer?

6.4 mil

Post by Richard Wilbur
5. What is the height of insulator between bottom layer and adjacent
ground reference layer?

6.4 mil.

standard 6 layer stack basically.

l.

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[Richard Wilbur]

On Thu, Jul 20, 2017 at 10:20 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
For our differential pairs we should only need one return-current-path
via per signal via (and hopefully relatively adjacent to it) since we
are using ground planes for our reference planes. It is basically
trying to provide a relatively low-impedance path for the RF
(radio-frequency) return current in the reference planes (since when
we switch signal layers between top and bottom, our reference plane
changes).

as best i can i've put the vias as close as possible. here's some new images
http://hands.com/~lkcl/eoma/a20_hdmi_review/

Thanks for the new pictures. I'll re-target my comments to address
the newest layout.

Post by Luke Kenneth Casson Leighton
i've also lined the bottom edge with vias, and there are a lot along
the top of the diff-pairs, separating other signals.

Thanks for all the dimensions.

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[Luke Kenneth Casson Leighton]

On Fri, Jul 21, 2017 at 4:59 PM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
http://hands.com/~lkcl/eoma/a20_hdmi_review/

Thanks for the new pictures. I'll re-target my comments to address
the newest layout.

appreciated. apologies for being curt the past couple days, long
days, very draining.

l.

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
apologies for being curt the past couple days, long
days, very draining.

Thank you for spearheading this project, for keeping at it when things got more complicated (because you now understood the problem better than at the outset), and for not giving up in the face of seemingly insurmountable obstacles (those are the problems we don't yet understand well enough to solve).

I especially enjoy working on hard problems because they are so rewarding to solve!

Thank you for the opportunity to collaborate on a project whose goals serve to advance the cause of freedom.

[Luke Kenneth Casson Leighton]

---
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On Sun, Jul 23, 2017 at 6:42 AM, Richard Wilbur

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton
apologies for being curt the past couple days, long
days, very draining.

Thank you for spearheading this project, for keeping at it when things got more complicated (because you now understood the problem better than at the outset), and for not giving up in the face of seemingly insurmountable obstacles (those are the problems we don't yet understand well enough to solve).
I especially enjoy working on hard problems because they are so rewarding to solve!

i know, right? :) this is why i picked it - there are a lot of
people doing things that can be done...

Post by Richard Wilbur
Thank you for the opportunity to collaborate on a project whose goals serve to advance the cause of freedom.

any time, very glad (and relieved) for your help.

l

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[Richard Wilbur]

Post by Luke Kenneth Casson Leighton
On Fri, Jul 21, 2017 at 4:59 PM, Richard Wilbur

Post by Richard Wilbur
Thanks for the new pictures. I'll re-target my comments to address
the newest layout.

appreciated.

What form would you prefer my recommendations take to make them most useful?
text,
Open Document Text (Open/Libre Office),
PDF

I have been writing them in Open Document Text format (Open/Libre
Office). The references are taken from freely available websites,
several of them documents in PDF (with helpful diagrams).

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On Mon, Jul 24, 2017 at 3:36 PM, Richard Wilbur

Post by Richard Wilbur
What form would you prefer my recommendations take to make them most useful?
text,

text is great ( to list here ) with online links to PDFs if there are any.

thanks richard.

l.

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[Luke Kenneth Casson Leighton]

hiya richard, i'd like to send off a test PCB to the factory with just
the DC3 micro-hdmi on it, whilst you're happily doing the review, can
i ask you the favour of checking to see if there's anything
glaringly-obvious about the DC3 layout (just the DC3 footprint
really).

i am aware that pins 8 and 12 are so close to the edge of the board
(with the 2 VIAs) that it's impossible to get GND shielding round
them... and that they're also doing a U-turn 180 degrees which is bad
for R.F.... but there's really not a lot of choice here.

at least they're surrounded by GND and vias... and... technically...
where the vias come up the pins for those signals are directly above
them (also surrounded by pins that are also GND)... so it's kiiinda
okay...

thoughts appreciated.

l.

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On Mon, Jul 31, 2017 at 1:42 PM, Richard Wilbur

Post by Luke Kenneth Casson Leighton
hiya richard, i'd like to send off a test PCB to the factory with just
the DC3 micro-hdmi on it, whilst you're happily doing the review, can
i ask you the favour of checking to see if there's anything
glaringly-obvious about the DC3 layout (just the DC3 footprint
really).

Sure! Sorry I haven't gotten my recommendations off to you earlier. I was hoping to finish a second draft of the document today after adding some discussion of the motivation for why I'm recommending certain things and not worrying about others. Then I was planning on firing it off to the list.
So I'll see how quickly I can change this from a waiting game to a technical discussion (dealing with DC3 pins 8 and 12 among other things).

appreciated. it's been about six weeks now, and there will be about
2 weeks estimated time on the test PCB before a 2.7.5 pre-production
test run could go ahead.

l.

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[Luke Kenneth Casson Leighton]

On Tue, Jun 27, 2017 at 4:56 AM, Richard Wilbur

Post by Richard Wilbur
1. Is there a publicly-accessible spot from which I can download the schematics and pcb files? (I found http://rhombus-tech.net/allwinner_a10/pcb/ is that the correct place?)

not yet.

Post by Richard Wilbur
2. How many copper layers does this board have?

6

Post by Richard Wilbur
3. What is the minimum trace size?

5mil

Post by Richard Wilbur
4. What is the minimum trace spacing?

5mil.

Post by Richard Wilbur
5. Is the minimum plated through hole diameter 6 mil?

yes. with a 12mil surround.

Post by Richard Wilbur
6. Did this message (composed on my iPhone E-mail client) come through in HTML or simple text?

no idea.

Post by Richard Wilbur
The Amphenol part has 0.15mm clearance between lands for even row of pins and board edge in cutout while Molex 468753011 has 0.9mm clearance in the same spot.

i'll be using the JAE DC3 because the pins are exposed, meaning that
standard oven baking can be used. the amphenol part the pins are
covered over, meaning that a second pass of solder reflow is needed.
that costs money... and sometimes doesn't work anyway.

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[Richard Wilbur]

On Thu, Jul 20, 2017 at 10:07 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Tue, Jun 27, 2017 at 4:56 AM, Richard Wilbur

[...]

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
2. How many copper layers does this board have?

6

Okay, that didn't change since the last time you answered this. (You
just answered the more complete version of my reply sent back on 27
Jun. I accidentally sent it before I finished writing it--and then
sent the complete version after I finished writing it. You replied in
June to the incomplete version of the message and today to the
complete version. Sorry for causing any confusion as I am still
making peace with the user interface of my smart phone E-mail
client--which I'm thankfully not using right now.)

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
3. What is the minimum trace size?

5mil

Post by Richard Wilbur
4. What is the minimum trace spacing?

5mil.

Did you change pcb fabricators recently? In June you said the minimum
trace size and spacing were 3.5mil. Just want to be sure I'm working
with the right numbers.

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
5. Is the minimum plated through hole diameter 6 mil?

yes. with a 12mil surround.

[...]

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
The Amphenol part has 0.15mm clearance between lands for even row of pins and board edge in cutout while Molex 468753011 has 0.9mm clearance in the same spot.

i'll be using the JAE DC3 because the pins are exposed, meaning that
standard oven baking can be used. the amphenol part the pins are
covered over, meaning that a second pass of solder reflow is needed.
that costs money... and sometimes doesn't work anyway.

Sounds like an improvement in manufacturability. Which part are you using?
These are all mid-mount micro-HDMI receptacles.

part number mounting depth Shell DIP length(mm)
DC3R019JA1R1500 0.95mm 1.2
DC3R019JA5R1500 0.95mm 0.8
DC3R019JA7R1500 0.65mm 0.65

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On Thu, Jul 20, 2017 at 10:35 PM, Richard Wilbur

Post by Richard Wilbur
On Thu, Jul 20, 2017 at 10:07 AM, Luke Kenneth Casson Leighton

Post by Luke Kenneth Casson Leighton
On Tue, Jun 27, 2017 at 4:56 AM, Richard Wilbur

[...]

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
2. How many copper layers does this board have?

6

Okay, that didn't change since the last time you answered this. (You
just answered the more complete version of my reply sent back on 27
Jun. I accidentally sent it before I finished writing it--and then
sent the complete version after I finished writing it. You replied in
June to the incomplete version of the message and today to the
complete version. Sorry for causing any confusion as I am still
making peace with the user interface of my smart phone E-mail
client--which I'm thankfully not using right now.)

i had a pre-prepared response which i'd not sent. saw the questions,
answered them, hit send... then realised i'd seen them before :)

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
3. What is the minimum trace size?

5mil

Post by Richard Wilbur
4. What is the minimum trace spacing?

5mil.

Did you change pcb fabricators recently?

no.

Post by Richard Wilbur
In June you said the minimum
trace size and spacing were 3.5mil.

yep that's another board.

Post by Richard Wilbur
Just want to be sure I'm working
with the right numbers.

5mil.

Post by Richard Wilbur

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
5. Is the minimum plated through hole diameter 6 mil?

yes. with a 12mil surround.

[...]

Post by Luke Kenneth Casson Leighton

Post by Richard Wilbur
The Amphenol part has 0.15mm clearance between lands for even row of pins and board edge in cutout while Molex 468753011 has 0.9mm clearance in the same spot.

i'll be using the JAE DC3 because the pins are exposed, meaning that
standard oven baking can be used. the amphenol part the pins are
covered over, meaning that a second pass of solder reflow is needed.
that costs money... and sometimes doesn't work anyway.

Sounds like an improvement in manufacturability. Which part are you using?
These are all mid-mount micro-HDMI receptacles.

correct.

Post by Richard Wilbur
DC3R019JA7R1500 0.65mm 0.65

this one lines up with the micro-hdmi and usb-otg connector.

l.

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[r***@Safe-mail.net]

Post by Luke Kenneth Casson Leighton
SoC, the RK3388 (yes it really does exist). also i'm waiting for some

Was it not rk3399?

Post by Luke Kenneth Casson Leighton
http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook

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[Luke Kenneth Casson Leighton]

Post by r***@Safe-mail.net
Was it not rk3399?

no it's an as-yet unannounced SoC, i met someone at computex who
showed me a prototype board with this chip on it, so i know it's
definitely named RK3388 and not anything else.

l.

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p.s. ron, well done for trimming unnecessary context.
l.

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[zap]

Post by Luke Kenneth Casson Leighton

Post by r***@Safe-mail.net
Was it not rk3399?

no it's an as-yet unannounced SoC, i met someone at computex who
showed me a prototype board with this chip on it, so i know it's
definitely named RK3388 and not anything else.

Ah that makes a lot of sense. Thank you, do you know when it will be
released?

Post by Luke Kenneth Casson Leighton
l.
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[Luke Kenneth Casson Leighton]

Post by zap

[... RK3388 ...]

Ah that makes a lot of sense. Thank you, do you know when it will be
released?

not at all.

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