Luke Kenneth Casson Leighton
2017-05-20 21:05:45 UTC
http://elinux.org/Embedded_Open_Modular_Architecture/CompactFlash#Table_of_EOMA-CF_pinouts
if you recall, someone kindly pointed out that USB3.1 does *not* need
two sets of Tx/Rx differential pairs but only one. so ironically that
means that four pins on an extremely low pincount standard are now
free. i thought, "ah ha! should add a 2nd USB2 to EOMA50!"
... but should it?
one of the things about SoCs that are that small, they can fit onto a
43x30mm PCB is: the probability of the pincount being high enough for
them to have two USB2 interfaces is... debatable. the GR8 definitely
does but that's just one SoC. and if it *doesn't*... then fitting a
USB hub on there to provide two USB2 interfaces is going to be a
bitch-and-a-half.
also, two new pins are definitely free: "by default" i would make
those EINT2 and EINT3 *but* the other option is to make them SPI data
lines 2 and 3 (for 4-bit DDR SPI).
choices, choices... i'm leaning towards 2 extra EINTs particularly as
i have an idea in mind for a modular smartphone, and the addition of
extra EINT-capable GPIO would allow a sub-module standard which has an
EINT line "per module". mind you a break-out GPIO device (such as oo
i dunno... a $1 STM32F!) is probably going to be needed for that
design concept anyway. bizarre, isn't it: you can either choose a
$1.50 dedicated GPIO breakout IC which only has 12 pins... or you can
choose a $1 EC which has 32 or 48 pins and has GPIO, USB, SPI, ADC,
DAC, I2C, UART... so bizarre.
anyway.
thoughts appreciated.
l.
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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if you recall, someone kindly pointed out that USB3.1 does *not* need
two sets of Tx/Rx differential pairs but only one. so ironically that
means that four pins on an extremely low pincount standard are now
free. i thought, "ah ha! should add a 2nd USB2 to EOMA50!"
... but should it?
one of the things about SoCs that are that small, they can fit onto a
43x30mm PCB is: the probability of the pincount being high enough for
them to have two USB2 interfaces is... debatable. the GR8 definitely
does but that's just one SoC. and if it *doesn't*... then fitting a
USB hub on there to provide two USB2 interfaces is going to be a
bitch-and-a-half.
also, two new pins are definitely free: "by default" i would make
those EINT2 and EINT3 *but* the other option is to make them SPI data
lines 2 and 3 (for 4-bit DDR SPI).
choices, choices... i'm leaning towards 2 extra EINTs particularly as
i have an idea in mind for a modular smartphone, and the addition of
extra EINT-capable GPIO would allow a sub-module standard which has an
EINT line "per module". mind you a break-out GPIO device (such as oo
i dunno... a $1 STM32F!) is probably going to be needed for that
design concept anyway. bizarre, isn't it: you can either choose a
$1.50 dedicated GPIO breakout IC which only has 12 pins... or you can
choose a $1 EC which has 32 or 48 pins and has GPIO, USB, SPI, ADC,
DAC, I2C, UART... so bizarre.
anyway.
thoughts appreciated.
l.
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Send large attachments to arm-***@files.phcomp.co.